LS 74139 Search Results

SC11091

Abstract: SC11064 SSI 7200 SC11091CV SC11091C SC11091CQ mc9346n sc11061 SC11011 sw 2604 ic schematic
Contextual Info: SIERRA SEMICONDUCTOR CORP SIERRA SEMICONDUCTOR SHE D • 0242010 0 0 0 2 2 flb 'T-lS-'bir^O SC11091/SC11095 2400 bps Universal Modem Advanced Controller □ Reverse compatible w ith SC11011,21,61 □ Direct interface to SCI 1006, SC11024, SC11026, SC11044,

74139

Abstract: LS 74139 74139 dual 2 to 4 data sheet 74139 S2090
Contextual Info: - M O - Dual 2 to 4 Demultiplexers 74139 DATA OUTPUTS V çç 2G 2A / 2Y0 . L VO 2V 1 L VT 2V2 L 2Y 3 N I Y 3 D-l niiUMlnkiÂïr IG 1A IB 1V0 1Y 1 1V2 1V3 GNO DATA OUTPUTS o-t u 7 h cob# , L l - 't £ > LS ALS S AS AC HC HCU HOT BC tpd max E-NABLE yo—Y7 32

ic 74139

Abstract: ic 74139 decoder pin diagram decoder IC 74139 74139 ic features of ic 74139 74139 decoder chip pinout 74HCxx of ic 74139 ic 74139 decoder 74139 pin diagram
Contextual Info: 33 H a r r is HPL -Q2C139 o> CO O <M CO Programmable Chip Select Decoder PCSD • Memory or I/O Chip Select Decoding, Replaces 2-3 ICs T O P VIEW • Similar to Industry Standard 74139 A C 1 16 3 • Microprocessor Bus Oriented Interface lb n 2 15 3 ŸÔ

ic 74139 decoder pin diagram

Abstract: 74139 pin diagram ic 74139 74139 decoder chip pinout decoder 74139 74139 decoder IC 74139 features of ic 74139 74139 decoder CI 74139
Contextual Info: S I h a r r is H P L -Q 2 C 1 3 9 Programmable Chip Select Decoder PCSD Pinout Features • T O P V IE W Mem ory o r I/O C hip Select Decoding, Replaces 2-3 ICs • S im ilar to Ind ustry Standard 74139 A • A rchitectu re O ptim ized fo r “ Bootstrap D ecoding"

ic 74138 pin diagram

Abstract: 74138 PIN DIAGRAM 74139 pin diagram 74138 OCTAL decoder ic 74139 ic 74139 decoder pin diagram ic 74138 gl520 74139 ic 74139 decoder chip pinout
Contextual Info: H a r r is HPL-82C339 Programmable Chip Select Decoder PCSD F eatures • • • • • • • • • • Pinouts Memory or I/O Chip Select Decoding, Replaces 3-7 ICs Superset of the Industry Standard 74138/74139 Microprocessor Bus Oriented Interlace

ic 74139

Abstract: ic 74139 decoder pin diagram 74139 ic LS 74139
Contextual Info: 33 Harris H P L -Q 2 C 1 3 9 Programmable Chip Select Decoder PCSD Features • Pinout TO P VIEW M em ory or I/O C h ip S elect D ecoding, Replaces 2-3 ICs • Sim ilar to Industry Standard 74139 A C I 16 D • M icroprocesso r Bus O riented Interface

ic 74139 decoder pin diagram

Abstract: ic 74139 decoder IC 74139 74139 ic
Contextual Info: CSD H a r r i s HPL-82C339 Programmable Chip Select Decoder PCSD Features Pinouts • M em o ry or I/O C h ip S elect D ecoding, R eplaces 3-7 ICs TO P VIEW • Superset of the Industry S tandard 7 41 38/74139 • M icroprocessor Bus O riented Interface

ic 74138 pin diagram

Abstract: IC 74138 74138 ic diagram ic 74139 decoder pin diagram ic 74139 74138 OCTAL decoder decoder IC 74138 of ic 74138 74138 IC decoder IC 74139 pin diagram
Contextual Info: h a r r is H PL-Q 2C 339 Programmable Chip Select Decoder PCSD Features • • • • • • • • • • Pinouts Memory or I/O Chip Select Decoding, Replaces 3-7 ICs Superset of the Industry Standard 74138/74139 Microprocessor Bus Oriented Interlace

74139

Abstract: 25LS2539 LS 74139 74139 dual 2 to 4 74539
Contextual Info: 74539 25LS2539 T in iiT ir E r ffT z n z r r a w ^ 2V. 2Yì ZV. 2P0L 2 0 E lA IB ofb üh%¿ o 3 T — I- it tj ;ii OK POL H X L L K X •Y« High Z L L H L H H H> a Y¡ 11 1 1Y' 1 Y. GND - 249- Dual 2 to 4 Demultiplexers (3-State) tpd tpd max A * E max A. B

sn 74373

Abstract: SN 74114 logic diagram of ic 74112 IC 7486 xor IC 7402, 7404, 7408, 7432, 7400 7486 xor IC sn 74377 IC TTL 7486 xor IC TTL 7495 diagram and truth table IC 74374
Contextual Info: PLS-WS/SN MAX+PLUS II Programmable Logic Software for Sun Workstations Data Sheet September 1991, ver. 1 Features J J □ □ □ J □ IJ Softw are supp ort for Classic, M A X 5000, M A X 7000, and S T G EPLD s Runs on Sun S P A R C s ta tio n s with S u n O S version 4.1.1 or h igher

Contextual Info: SC11091/SC11095 2400 bps Universal Modem Advanced Controller SIERRA SEMICONDUCTOR □ R everse c o m p a tib le w ith □ S u p p o rts M N P 2 -5 a n d CCITT □ □ □ □ □ □ □ □ □ 9 1 61 ^Q.r\rtnnnrkfin SC 11011,2 1,61 D irect in terface to SC11006,

0221l

Abstract: APPLICATION NOTES CD 7474 IC bit-slice TGC119 TGC100 IPF 830 RC02X ci 7432 ttl DTN20 tsg 271
Contextual Info: TGC100 Series 1-|im CMOS Gate Arrays RELEASE 4.0. REVISED SEPTEMBER 1991 14 Arrays with up to 26K Available Gates C E LL C O LU M N Fast Prototype Turnaround Time W IR IN G C H A N N E L Extensive Design Support -Design Libraries Compatible With Valid,u and Mentor CAE Systems

SN76477

Abstract: TNY 176 PN EQUIVALENT 2n4401 free transistor equivalent book tis43 XR2206 application notes Semiconductor Data Handbook mj802 2N3866 s2p bc149c TIP35C TIP36C sub amplifier circuit diagram LM131
Contextual Info: From the Publishers of ETI & HE HEM M iNqs E U c t r o n ic s L rd Electronic C om ponents Et M icrocom puters 16 BRAND STREET, HITCHIN, HERTS, SG5 1JE Telephone: 0462 33031 memories 2114L 2708 2716 2532 2732 4116 4164 6116P3 6116LP3 •Op 220p 210p 380p

7408 CMOS

Abstract: TTL 7452 ttl 74183 LS 74141 7408, 7404, 7486, 7432 7404 7408 7432 TTL 74289 74106 CMOS 4017 series ttl 74395
Contextual Info: KG10000 SERIES SEMI-CUSTOM CMOS GATE ARRAY CMOS SILOCON GATE ARRAY Th e KG10000 S e rie s is c o n sists o f s ilico n gate C M O S arrays w hose inte rco n n e ctio n are in itia lly u n s p e c ifie d , th e re fo re custom LSI is p ro ce sse d w ith o n ly one m ask ste p a cu sto m ize d m etal m ask a c c o rd ­

74138 decoder

Abstract: 74139 decoder 74139 pin diagram SCM-101 decoder 74139 SCM100B datel scm-101 AS-002 AO SCM-100A 74138 logic circuit
Contextual Info: DATEL INC 07E D • S b 51S b 1 00D10D4 3 ■ SCM -100, SCM-101 Four-Channel, Isolated Signal Conditioning M odules E D M T ÎE L T -7} - n - o i FEATURES • Wide input span range « 4-Channel operation • ±1000 Volts peak Isolation voltage • 1S6 dB CMR

74139 demultiplexer

Abstract: 74169 SYNCHRONOUS 4-BIT BINARY COUNTER pin diagram 41 multiplexer 74153 3-8 decoder 74138 pin diagram bcd counter using j-k flip flop diagram pin diagram priority decoder 74148 CI 74151 74181 74175 clock 74165 block diagram 74151 demultiplexer
Contextual Info: M OIVIOUOUU, s em i c onductor GENERAL DESCRIPTION FEATURES The OKI MSM60300, MSM60700. and MSM61000 gate arrays are fabricated using state-of-the-art 3/i dual-layer metal silicon gate CMOS technology. A unit cell consists of 4 pairs o f transistors where each pair is made up of a PMOS and a NMOS transistor.

asynchronous 4bit up down counter using jk flip flop

Abstract: counter 74168 Multiplexer 74152 3-8 decoder 74138 synchronous counter using 4 flip flip 74183 alu 7444 series Excess-3-gray code to Decimal decoder MH 74151 counter 74169 74169 SYNCHRONOUS 4-BIT BINARY COUNTER
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T his series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

pin diagram AMD FX 9590

Abstract: Transistor AF 138 laser sharp measurement d6406 pby 283 diode data book SN74298
Contextual Info: V o lu m e 5 $5.00 Harris Semiconductor Sector Capabilities Harris Semiconductor, one of the top ten U.S. merchant semiconductor suppliers, is a sector of Harris Corporation — a producer of advanced information processing, communication and microelectronic

74LS82

Abstract: 74245 BIDIRECTIONAL BUFFER IC ic 4583 schmitt trigger core bit excess 3 adder using IC 7483 advantages for ic 7473 4 BIT COUNTER 74669 la 4508 ic schematic diagram XF107 74295 random number generator by using ic 4011 and 4017
Contextual Info: General Features The SCxD4 series of high performance CMOS gate arrays offers the user the ability to realise customised VLSI inte­ grated circuits featuring the speed performance previously obtainable only with bipolar technologies whilst retaining all the advantages of CMOS technology; low power consum p­

16CUDSLR

Abstract: 7474 D flip flop free alu 74382 counter schematic diagram 74161 sn 74373 pin diagram of ic 74190 ALU IC 74381 HFJV1 MUX 74151 IC 74373 truth table
Contextual Info: PLDS-MAX & PLS-MAX M MAX+PLUS Program mable Logic Developm ent System & Software M Data Sheet September 1991, ver. 1 □ □ □ □ □ □ □ □ □ S o ftw a re su p p o rt for M A X 5000 M u ltip le A rray M atriX E PL D s H ierarch ical d esig n entry m eth o d s for b oth g rap h ic and text d esig n s

Contextual Info: SC11091/SC11095 2400 bps Universal Modem Advanced Controller SIERRA SEMICONDUCTOR □ Supports SD L C , H D L C , Bisync, M onosync & A sync protocols in softw are □ Reverse com patible w ith S C I 1011,21, 61 □ D irect interface to S C I 1006, SC11024, SC11026, SC11044,

74ls82

Abstract: 74245 BIDIRECTIONAL BUFFER IC 74ls150 ph 4531 diode 4583 dual schmitt trigger ic D flip flop 7474 74245 BUFFER IC ic 7483 BCD adder data sheet ic 74139 Quad 2 input nand gate cd 4093
Contextual Info: General Features The SCxD4 series of high perform ance CM O S gate arrays offers the user the ability to realise custom ised VLSI inte­ grated circuits featuring the speed perform ance previously obtainable only with bipo lar tech nolog ies whilst retaining all

counter 74168

Abstract: 3-8 decoder 74138 counter 74169 Multiplexer 74152 74183 adder 74381 alu 74169 binary counter 74151 8 by 1 Multiplexer flip flop 74379 74175 flip flops
Contextual Info: • GENERAL DESCRIPTION T h e M S M 7 0 V 0 0 0 series is the gate array LSI based on the m aster slice m e th o d using the high p erfo rm an ce silicon gate 1.5 m ic ro n H C M O S process w ith th e d u a l-la y e r m etal structure. T h is series has th e features to easily realize fu n c tio n s o f th e s c h m itt trigger, c ry s ta l/

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers