LOGIC SYMBOL 74S Search Results

7405 power regulator

Abstract: TL 7805 common anode 7 segment tl 7805 l 5V power supply using bridge circuit using 7805 MA 7805 7805 national semiconductor FULL WAVE RECTIFIER CIRCUITS dual 7 segment led display 7805 datasheet
Contextual Info: DM9374 7-Segment Decoder Driver Latch with Constant Current Sink Outputs General Description The ’74 is a 7-segment decoder driver incorporating input latches and output circuits to directly drive common anode LED displays Connection Diagram Logic Symbol

7405 power regulator

Abstract: 7805 connection with full wave rectifier 18 pin dual 7-SEGMENT LED DISPLAY 7405 truth table dtl 9936 common anode 7 segment DM9374 common anode 7-segment free voltage regulator 7805 5V power supply using bridge circuit using 7805 d
Contextual Info: DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs LED displays. General Description The ’74 is a 7-segment decoder driver incorporating input latches and output circuits to directly drive common anode Connection Diagram Logic Symbol

74157PC

Contextual Info: 157 CONNECTION DIAGRAM PINOUT A '54/74157 O U l c l - l 54S/74S157 o n I S I 54LS/74LS157 0 /// s ° QUAD 2-INPUT MULTIPLEXER LOGIC SYMBOL DESCRIPTION — The '157 isa high speed quad2-inputmultiplexer. Fourbits of data from two sources can be selected using the common Select and En­

Excess-3

Abstract: s5443f N7443F N7443N S5443W
Contextual Info: LOGIC SYMBOL 54/7443 DESCRIPTION T h e '‘43 " is a T T L M SI a rra y utilized in d e ­ coding and logic co nversion ap p licatio ns. Th e “ 4 3 ” d e c o d e s e x c e s s - 3 co d e numbers to 1-of-10 outputs. 3 PIN CONFIGURATION ORDERING CODE PA CK A G ES

74LS78

Contextual Info: 54LS/74LS78 LOGIC SYMBOL DESCRIPTION The “ 78” is a Dual JK Negative EdgeTriggered Flip-Flop featuring individual J, K, Set, common Clock and common Reset inputs. The Set Sd and Reset (Rd > inputs, when LOW, set or reset the outputs as shown in the Truth Table regardless of the

Contextual Info: LOGIC SYMBOL 5 4 /7 4 2 5 9 — See 9334 54LS /74LS 259 Prelim inary data DESCRIPTION FEATURES The “259" is an 8-Bit Addressable Latch with these control inputs; three Address in­ puts (Aq, A i , A2 ), an active LOW Enable input (E) and an active LOW Clear input

74LS289

Abstract: N74LS289F N74LS289N
Contextual Info: 54S/74S289 3101A 54LS/74LS289 (Preliminary data) LOGIC SYMBOL See Slgnetics Memory Data Manual for 3101A Specifications DESCRIPTION FEATURES T h e " 2 8 9 " is a 6 4 - B it h ig h - s p e e d R ead /W rite Random A c c e s s M em ory for use a s a "sc ra tc h pad" memory with non­

Contextual Info: 54LS/74LS299 LOGIC SYMBOL DESCRIPTION FEATURES The "299" Is an 8-Bit Bidirectional Universal S h ift/S to ra g e R e g iste r w ith a 3 -sta te bidirectional Input/Output port. The register has four operating modes: shift right, shift left, parallel load, and hold do nothing . The

N74H71F

Abstract: N74H71N S54H71F S54H71W so 54 t
Contextual Info: 54H/74H71 LOGIC SYMBOL s A DESCRIPTION The “ 71 ” is a positive puise triggered master slave flip -flo p with AND-OR gated JK in­ puts and direct Set Sd input. JK inform a­ tion is loaded into the master while the Clock is HIGH and transferred to the slave

74151APC

Abstract: 54151A
Contextual Info: 151 CONNECTION DIAGRAM PINOUT A / o f o^i 7 ^ v 54/7415TAx y54S/74S151 O ! o r y ° f V 5 4 L S /7 4 L S 1 5 1 ^ ^ ^ ^ 8-INPUT MULTIPLEXER LOGIC SYMBOL DESCRIPTION — The '151 is a high speed 8-input digital multiplexer. It pro­ vides in one package, the ability to select one line of data from up to eight

ic 74198

Abstract: sn 74198 74198
Contextual Info: LOGIC SYMBOL 54/74198 3 DESCRIPTION FEATURES The “ 198” is a 8 -Bit B idirectio nal Universal Shift R egiste r useful in a w ide varie ty of a p ­ plications. As a high speed m ultifunctional sequential building block, it may be used in seria l-seria l, s eria l-pa rallel, pa rallel-se rial,

Contextual Info: 5477 54LS77 DESCRIPTION LOGIC SYMBOL FEATURES The “ 7 7 " is a Dual 2-Bit D -Latch offe re d in a 14-Pin fla t pack. Two Enable inputs are pro­ vided; each con trols tw o latches. When the Enable E is HIGH, inform ation present at a Data (D ) input is tra nsferred to th e Q o u t­

54LS

Abstract: 74LS N74LS299F N74LS299N S54LS299F 74LS299 APPLICATIONS
Contextual Info: LOGIC SYMBOL 54LS/ 7 4LS299 DESCRIPTION FEATURES The "2 9 9 ” is an 8 -Bit B idirectional Universal S h ift/S to r a g e R e g is te r w ith a 3 -s ta te bidirection al Inp ut/O u tput port. The re gister has four operating modes: shift right, shift left, parallel load, and hold do nothing . The

Contextual Info: LOGIC SYMBOL 5 4 /7 4 1 9 0 54LS/74LS 190 DESCRIPTION FEATURES The “ 190’' is a pre s e tta b le B C D /D e cade U p/D ow n Counter w ith sta te changes of the counter synchronous w ith the LOW-to-HIGH transition of the C lock Pulse input. • The c ircu it features an asynchronous P aral­

74LS78

Abstract: N74LS78F N74LS78N S54LS78F S54LS78W
Contextual Info: 54LS/74LS78 LOGIC SYMBOL DESCRIPTION T he “ 78” is a D ual JK N egative EdgeT rig g e re d F lip-F lo p fe a tu rin g individual J, K, Set, com m on C lock and com m on Reset inputs. The Set <Sd > and Reset R d > inpu ts, w hen LOW , set o r reset th e o u tp u ts as

N74S89N

Abstract: N74LS89F N74LS89N N74S89F S54LS89F S54S89F
Contextual Info: 54S/74S89 54LS/74LS89 Preliminary LOGIC SYMBOL data FEATURES DESCRIPTION T h e ''S S }" is a 6 4 -B it h ig h -s p e e d R e a d / W r it e R a n d o m A c c e s s M e m o r y fo r u s e a s a “s c r a t c h p a d 1’ m e m ory with n o n -d e stru c tiv e

74LS73

Abstract: pin diagram of 7473 74LS73 dual JK 74H73 7473 JK flip flop 7473 pin diagram 7473 Flip-Flop 7473 N7473F N7473N
Contextual Info: 54/7473 54H/74H73 54LS/74LS73 LOGIC SYMBOL 14 — DESCRIPTION 12 1 -0 > C P J O 13 10 - IO — ¥ IO 3 — Q The Reset R d is an a syn ch ro n o u s active LO W input. W hen LOW, it ove rrides the C lock and data inpu ts fo rc in g the Q o u tp u t LO W and the Q o u tp u t HIGH.

74H101

Abstract: N74H101F N74H101N S54H101F S54H101W
Contextual Info: 54H/74H101 LOGIC SYMBOL A 5 DESCRIPTION The “ 101” is a JK N egative E dge -T rig gere d F lip-F lo p fe a tu rin g A N D -O R gated_JK in­ puts and a d ire c t Set inpu t. Th e Set S d is an a s y n c h ro n o u s active LOW input. W hen LOW, the So ove rrides th e c lo c k and data

Flip-Flop 7470

Abstract: N7470F 7470 flip flop N7470N S5470F S5470W 7470 pin diagram
Contextual Info: LOGIC SYMBOL 54/7470 DESCRIPTION The 54/7470 is a positive e d g e -trig g e re d J-K F lip-F lo p fe a tu rin g d ire c t Set and Reset jn p u ts and c o m p le m e n ta ry o u tp u ts Q and Q. In fo rm a tio n is tra n s fe rre d to th e o u tp u ts on the L O W -to-H IG H tra n s itio n o f the C lock

7480 full adder 1 bit

Abstract: 7480 ADDER N7480F ttl 7480 AZ41 74LS N7480N S5480F S5480W circuit diagram of inverting adder
Contextual Info: 54/7480 LOGIC SYMBOL a DESCRIPTION FEATURES T h e “ 8 0 ” is a G a te d Full A d d e r u se fu l fo r p a ra lle l o r s e ria l a d d itio n and fo r a d d itio n o f m o re th a n tw o v a ria b le s . It fe a tu re s g a te d c o m p le m e n ta ry in p u ts , c o m p le m e n ta ry sum

MAX2333

Abstract: T-66-21 L67H 74ls251pc
Contextual Info: NATIONAL SEMICOND {LOGIC} DEE D | bSOllES D O L ^ S S 0 | _ T-66-21 -53 251 CONNECTION DIAGRAM PINOUT A - 54S/74S251 54LS/74LS251 in v c c ijÖi« m is »E l2[? 8-INPUT MULTIPLEXER With 3-State Outputs Ii[3 loE

Contextual Info: NATIONAL SEMCOND {LOGIC} DHE D | bSOllSS □ D b 3 TSÖ 253 b | T -6 6 -2 1 -5 3 CO NNECTION DIAGRAM PINOUT A 54S/74S253 54LS/74LS253 DUAL 4-INPUT MULTIPLEXER With 3-State Outputs DESCRIPTION — The ’253 Is a dual 4-input multiplexer with 3-state outputs.

74LS158PC

Abstract: 74S158PC Z1212 54LS158DM 54S158DM 74LS158DC 74LS158FC 74S158DC 74S158FC 74LS158D
Contextual Info: 1 NATIONAL SEdlCOND {LOGIC} DEE D | bS01122 DQb3fi47 ö | _ T-66-21-53 158 CONNECTION DIAGRAM PINOUT A 54S/74S158 54LS/74LS158 •E nr haE QUAD 2-INPUT MULTIPLEXER TÏ1 v c c ioa Ts] ë 2a [ I Í3 ]l,c lo b [s 2]ZC H ]lo c lod lib [ I

74LS139PC

Abstract: 74LS139P 74LS139DC
Contextual Info: ;'1 NATIONAL SEMICOND -CLO.GIO OSE D | bSDllPS 00b3fll? D | 139 139 T-66-21-55 CONNECTION DIAGRAM P IN O U T 54S/74S139 54LS/74LS139 A o a [I i s ] Eb A la [ 7 Î 7 ] Aob Öoa [ T 75] 1 2 ]Ö 0 b Ö 2a [ ? T ijö ib Ô 3 a [T 10] 5 2 b [? ~9~1 0 3 b DESCRIPTION — The *139 is a high speed dual t-of-4 decoder/demulti­