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    N74H71N Search Results

    N74H71N Datasheets (2)

    Signetics
    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    N74H71N
    		Signetics JK Pulse Triggered Flip-Flop Scan PDF 76.59KB 2
    N74H71N
    		Signetics Integrated Circuits Catalogue 1978/79 Scan PDF 906.06KB 27
    SF Impression Pixel

    N74H71N Price and Stock

    Texas Instruments

    Texas Instruments SN74H71N1

    J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, PDIP14
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian SN74H71N1 8,632
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    Texas Instruments SN74H71N-00

    J-K Flip-Flop, TTL/H/L Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14
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    Vyrian SN74H71N-00 8,597
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    Texas Instruments SN74H71N

    J-K Flip-Flop, TTL/H/L Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian SN74H71N 8,143
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    Texas Instruments SN74H71N3

    J-K Flip-Flop, 1-Func, Master-slave Triggered, TTL, PDIP14
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian SN74H71N3 7,881
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    Texas Instruments SN74H71N-10

    J-K Flip-Flop, TTL/H/L Series, 1-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, PDIP14
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Vyrian SN74H71N-10 6,122
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    N74H71N Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    74H Logic Family Specifications

    Abstract: N74H71F N74H71N S54H71F S54H71W
    Contextual Info: s A DESCRIPTION T he “ 71 ” is a positive pulse trig g e re d m aster slave flip -flo p w ith A N D -O R gated JK in­ puts and d ire c t Set S d input. JK in fo rm a ­ tio n is loaded in to th e m a ster w h ile the C lo ck is H IG H and tra n s fe rre d to th e slave


    OCR Scan     		54H/74H71 54H/74H 54S/74S 54LS/74LS 74H Logic Family Specifications N74H71F N74H71N S54H71F S54H71W PDF

    N74H71F

    Abstract: N74H71N S54H71F S54H71W so 54 t
    Contextual Info: 54H/74H71 LOGIC SYMBOL s A DESCRIPTION The “ 71 ” is a positive puise triggered master slave flip -flo p with AND-OR gated JK in­ puts and direct Set Sd input. JK inform a­ tion is loaded into the master while the Clock is HIGH and transferred to the slave


    OCR Scan     		54H/74H71 54H/74H 54S/74S 54LS/74LS N74H71F N74H71N S54H71F S54H71W so 54 t PDF