LOF ATM Search Results

THE ATM PHYSICAL LAYER

Abstract: Bellcore-GR-253 ATM circuit diagram TSOC PM5356 rfpo
Contextual Info: PM5356 S/UNI-622-MAX PMC-Sierra,Inc. 622 Mbit/s ATM Physical Layer Device FEATURES • Counts received section BIP-8 B1 , line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs. • Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI.

PM5356

Abstract: rfpo
Contextual Info: PMC-Sierra,Inc. PM5356 S/UNI-622-MAX Preliminary 622 Mbit/s ATM Physical Layer Device FEATURES • Counts received section BIP-8 B1 , line BIP-24 (B2), and path BIP-8 (B3) errors, and line and path FEBEs. • Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI and PERDI.

STM-1 Physical interface PHY

Abstract: LOF atm TNETA1500 TNETA1560 TNETA1561 loca RAM cells bit lines "select line" ATM SAR controller registers
Contextual Info: TNETA1500 SABRE Architecture SONET/SDH/ATM BICMOS Receiver Transmitter 4ATM@timsg.csc.ti.com < TNETA1500 Architecture Presentation 5/95 > AGENDA • Main features • Interfaces • Architecture • Transmit operation • Receive operation • Controller interface operation

TNETA1500A

Abstract: 822LY 622LY
Contextual Info: TNETA1500A 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS042A – AUGUST 1997 – REVISED JANUARY 1998 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte Asynchronous Transport Mode ATM Cells Via STS-3c/STM-1 Frame (155.52 Mbit/s) On-Chip Analog Phase-Locked Loop

TNETA1500A

Abstract: tsct 1000 622LY 822LY
Contextual Info: TNETA1500A 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS042A – AUGUST 1997 – REVISED JANUARY 1998 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte Asynchronous Transport Mode ATM Cells Via STS-3c/STM-1 Frame (155.52 Mbit/s) On-Chip Analog Phase-Locked Loop

TNETA1500A

Contextual Info: TNETA1500A 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS042A – AUGUST 1997 – REVISED JANUARY 1998 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte Asynchronous Transport Mode ATM Cells Via STS-3c/STM-1 Frame (155.52 Mbit/s) On-Chip Analog Phase-Locked Loop

78mHz

Abstract: U5A1
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet STS-48 Physical Layer ATM UNI/NNI Device VSC9110 Features • STS-48c ATM Framing Device for User Network Interface and Network Node Interface Applications • +3.3V Power Supply • STS-48c / STM-16c Support. Terminates and

ATM machine using microcontroller

Abstract: u 741 GR-253-CORE STS-48 STS-48C VSC9110
Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet STS-48 Physical Layer ATM UNI/NNI Device VSC9110 Features • STS-48c ATM Framing Device for User Network Interface and Network Node Interface Applications • +3.3V Power Supply • STS-48c / STM-16c Support. Terminates and

TNETA1500

Contextual Info: TNETA1500 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS021C – MARCH 1994 –REVISED JULY 1995 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte ATM Cells Via STS-3c/STM-1 Frame 155.52 Mbit /s On-Chip Analog Phase-Locked Loop (APLL) Provides:

622LY

Abstract: 822LY TNETA1500 19.44MHZ OSCILLATOR
Contextual Info: TNETA1500 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS021D – MARCH 1994 – REVISED JANUARY 1998 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte ATM Cells Via STS-3c/STM-1 Frame 155.52 Mbit/s On-Chip Analog Phase-Locked Loop

Contextual Info: TNETA1500 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS021D – MARCH 1994 – REVISED JANUARY 1998 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte ATM Cells Via STS-3c/STM-1 Frame 155.52 Mbit/s On-Chip Analog Phase-Locked Loop

TNETA1500A

Abstract: Alarm Clock by using ttl atm header-error-check multiple bit 622LY-221K ECE-A1AFS471
Contextual Info: TNETA1500A 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SD N S 042 - AUG UST 1997 • Single-Chip Receiver/Transmitter for Transporting 53-Byte Asynchronous Transport Mode ATM Cells Via STS-3C/STM-1 Frame (155.52 Mbit/s) • On-Chip Analog Phase-Locked Loop

622LY

Abstract: 822LY TNETA1500
Contextual Info: TNETA1500 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER SDNS021D – MARCH 1994 – REVISED JANUARY 1998 D D D D Single-Chip Receiver/Transmitter for Transporting 53-Byte ATM Cells Via STS-3c/STM-1 Frame 155.52 Mbit/s On-Chip Analog Phase-Locked Loop

"Overflow detection"

Contextual Info: µPD98413 NEASCOT-P65 QUAD 622M ATM/POS SONET FRAMER Draft specification rev0.2 Document No. 2SYSM-FAD-0081 Date Published October 2000 CP(K) NEC Corporation • The information contained in this document is being issued in advance of the production cycle for

t04 68 3 pin transistor

Abstract: MD 202 flame relay AC03 nec alps lcd 14 pin t04 68 3 pin diode transistor z5t S3043 S3044 STM-16 z046
Contextual Info: User’s Manual µPD98414 NEASCOT-P70TM ATM 2.4Gbps SONET Framer Document No. S14166EJ4V0UM00 (4th edition) Date Published December 2001 J CP(K) 1999 1991 Printed in Japan [MEMO] 2 User's Manual S14166EJ4V0UM SUMMARY OF CONTENTS CHAPTER 1 GENERAL .13

GG1Q

Contextual Info: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram o f the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission

TNETA1500A

Contextual Info: TNETA1500A 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER S D N S 042A - AUGUST 1 9 9 7 - REVISED JANUARY 1998 Single-Chip Receiver/Transmitter for Transporting 53-Byte Asynchronous Transport Mode ATM Cells Via STS-3c/STM-1 Frame (155.52 Mbit/s) On-Chip Analog Phase-Locked Loop

MB86683B

Abstract: NTC03001 NTC03002 NTC03003 NTC03004 NTC03005 NTC03006 SR58 SR59
Contextual Info: Deviation List MB86683B September 1996 Network Termination Controller NTC Version 7.0 FML/NPD/NTC/DL/1262 Identification Number NTC03001 Category DMA Controller Summary NSR timeout values can be inconsistent when small values are used. Description While DMA takes place, the NSR timer is held in a reset state. Therefore, if the DMA

n8223

Abstract: N-822 CN8223EPF AD6116 78P7200 CN8223 BT8222EPFE PROCESS CONTROL TIMER using 555 ic
Contextual Info: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI

bip 109

Abstract: 78P7200 CN8223 CN8223EPF
Contextual Info: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI

BT8222KPF

Abstract: atm header error checking 78P7200 CN8223 CN8223EPF e3 frame formatter
Contextual Info: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI

ATM machine using microcontroller

Contextual Info: VITESSE SEMICONDUCTOR CORPORATION Data Sheet STS-48 Physical Layer ATM UNI/NNI Device VSC9110 Features • STS-48c ATM Framing Device for User Network Interface and Network Node Interface Applications • +3.3V Power Supply • STS-48c / STM-16c Support. Terminates and

N8222

Abstract: 28-22-21 bt8222
Contextual Info: Bt8222 ATM Transmitter/Receiver with UTOPIA Interface The Bt8222 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI

VC4-16c

Abstract: ml 741 c GR-253-CORE STS-48 STS-48C VSC9110 PECL10
Contextual Info: SEMICONDUC TOR CORPORATION STS_48 physjca, Layer Target Specification VSC9110 atm UNI/NNI Device Features VITESSE CONFIDENTIAL • STS-48c ATM Framing Device for User Net­ work Interface and Network Node Interface Applications • +3.3V Power Supply • +5V Tolerant TTL I/O