LH522 Search Results

LH52256C-10LL

Abstract: LH525CL9 256k sram
Contextual Info: PRODUCT SPECIFICATIONS Integrated Circuits Group LH52256C-10LL 256K SRAM Model No.: LH525CL9 Spec No.: EL095120 Issue Date: June 2, 1997 Static SRAM RAM Random Access Memory LH52256C-10LL 256K (32Kx8) (100 ns) (DIP)

unit inch sdip28

Abstract: LH52256C lh52256c-70ll
Contextual Info: LH52256C/CH FEATURES • 32,768 x 8 bit organization • Access time: 70 ns MAX. CMOS 256K (32K × 8) Static RAM PIN CONNECTIONS TOP VIEW 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP • Supply current: Operating: 45 mA (MAX.) 10 mA (MAX.) (tRC, tWC = 1 µs) Standby: 40 µA (MAX.)

AS71

Contextual Info: LH52256AS PIN CONNECTIONS FEATURES • 32,768 x CMOS 256K 32K x 8 Static RAM 8 bit organization TO P VIEW 28-PIN SOP • Access time: 500 ns (MAX.) Z' 28 Ai2 C 2 27 □ WE 7 C 3 26 Zl A,3 Aß [Z 4 25 Z3 Ag a 18 mW (tRc, twc = 1 M-S (TYP.) Standby: 72 (MAX.)

LH52252

Abstract: lh52252b
Contextual Info: LH52252B FEATURES • Fast Access Times: 15/20/25 ns • Standard 24-Pin, 300-mil DIP • Space Saving 24-Pin, 300-mil SOJ • JEDEC Standard Pinouts • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation

Contextual Info: LH52252B FEATURES • Fast Access Times: 20/25 ns • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count • JEDEC Standard Pinouts • Packages: 24-Pin, 300-mil DIP 24-Pin, 300-mil SOJ

3114 sram

Contextual Info: SHARP CORP S1E D • AlflOTTA 0Q0bc!2A 70S B S R P J T -H 6 -Z 3 -I? PRELIMINARY LH52258B CMOS 32K x 8 Static RAM FEATURES FUNCTIONAL DESCRIPTION The LH52258B is a high speed 262,144 bit static RAM organized as 32K x 8. A fast, efficient design is obtained

Contextual Info: LH52258A CMOS 32K x 8 Static RAM When E is LOW and W is HIGH, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation, new Read cycles can be

LH52250

Abstract: SHARP 357 LH52250A LH52250AD-70L sop28
Contextual Info: LH52250AL FEATURES • Access Times: 70/100 ns • Automatic Power Down During Long Read Cycles • Low Power Standby W hen Deselected • T TL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • 2 V Data Retention • Packages: 28-Pin, 300-mil DIP

4108 RAM

Contextual Info: LH52256AS FEATURES CMOS 256K 32K x 8 Static RAM PIN CONNECTIONS • 32,768 × 8 bit organization • Access time: 500 ns (MAX.) 28-PIN SOP • Supply current: Operating: 36 mW (MAX.) 18 mW (tRC, tWC = 1 µs (TYP.) Standby: 72 µW (MAX.) TOP VIEW A14 1

Contextual Info: LH52256C/CH FEATURES CMOS 256K 32K x 8 Static RAM PIN CONNECTIONS • 32,768 x 8 bit organization • Access time: 70 ns (MAX.) A -|2 c a7 10 mA (MAX.) (tRc, twc = "I l^s) Standby: 40 (iA (MAX.) = C 1• 28 ^ Vqq 2 27 □ WE 3 26 ^ A, 3 Ag C 4 • Data retention current: 1.0 (iA (MAX.)

LH52256CVJY

Contextual Info: PRODUCT SPECIFICATIONS Integrated Circuits Group LH52256CVJY 256K SRAM Model No.: LH525CV7 Spec No.: MS-J09902 Issue Date: October 16, 1997 CSP, Static, SRAM, RAM, Random Access Memory, LH52256CVJY

LH52256CN-85LL

Abstract: LH525C8N
Contextual Info: PRODUCT SPECIFICATIONS Integrated Circuits Group LH52256CN-85LL 256K SRAM Model No.: LH525C8N Spec No.: EL081072A Issue Date: May 24, 1996 STATIC SRAM RAM Random Access Memory Low Power SOP LH52256CN-85LL CMOS 256K (32K x 8)

Contextual Info: Static SRAM RAM Random Access Memory LH52256CH-85LL 256K 32Kx8 (85 ns) (DIP)

Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V± 10% Supply • Fully Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ CMOS 32K x 8 Static RAM

lh52256n-90

Contextual Info: CMOS 256K 32K x 8 Static RAM FEATURES DESCRIPTION • 3 2 ,7 6 8 x 8 bit organization The LH52256LL is an ultra-low power CMOS-periphery static RAM organized as 32,768 x 8 bits. It is fab­ ricated using silicon-gate CMOS process technology. • Access time:

Contextual Info: LH52253 FEATURES • Fast Access Times: 17/20/25/35 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation CMOS 64K X 4 Static RAM The LH52253 offers an Output Enable G for use in managing the Data Bus. Bus contention jluring Write

LH52258A

Abstract: SOJ8
Contextual Info: LH52258A FEATURES • Fast Access Times: 20/25 ns • Low-Power Standby when Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully-Static Operation • JEDEC Standard Pinout • Packages: 28-Pin, 300-mil DIP 28-Pin, 300-mil SOJ FUNCTIONAL DESCRIPTION

Contextual Info: LH52253 FEATURES • Fast Access Times: 20/25/35 ns • Low Power Standby when Deselected • TTL Compatible I/O • 5 V ± 1 0 % Supply • Fully Static Operation • Common I/O for Low Pin Count • JEDEC Standard Pinouts • Packages: 28-Pin, 300-mil DIP

Contextual Info: PRELIMINARY LH52258B CMOS 32K x 8 Static RAM FUNCTIONAL DESCRIPTION FEATURES The LH52258B is a high speed 262,144 bit static RAM organized as 32K x 8. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells.

LH52256N

Abstract: lh52256
Contextual Info: SHARP CORP S1E D • AlAD? OOdblftH bS3 M S R P J T - H C - 2 3 - /3 LH52256LL FEA TU R ES • 32,768 x 8 bit organization • Access time: 90 ns MAX. • • Low power consumption: Operating: 385 mW (MAX.) Standby: 220 (MAX.) Fully static operation • TTL compatible I/O

LH52252AD-35

Abstract: LH52252A LH52252 LH52252AD
Contextual Info: LH52252A FEATURES • Fast Access Times: 25/35/45 ns • Low Power Standby When Deselected • TTL Compatible I/O • 5 V ± 10% Supply • Fully Static Operation • Common I/O for Low Pin Count • JEDEC Standard Pinouts • Packages: 24-Pin, 300-mil DIP

LH52256C-70LL

Abstract: LH52256C
Contextual Info: LH52256C/CH FEATURES • 32,768 x 8 bit organization • Access time: 70 ns MAX. CMOS 256K (32K × 8) Static RAM PIN CONNECTIONS TOP VIEW 28-PIN DIP 28-PIN SK-DIP 28-PIN SOP • Supply current: Operating: 45 mA (MAX.) 10 mA (MAX.) (tRC, tWC = 1 µs) Standby: 40 µA (MAX.)

Contextual Info: PRODUCT SPECIFICATIONS Integrated Circuits Group LH52256CHN-70LL 256K SRAM Model No.: LH525C1N Spec No.: EL08Y160 Issue Date: November 26, 1996 LH525C1N 0 Handle this document carefully for it contains material protected by international of this material

MB84256-15LL

Abstract: M5M5256AP-70L M5M5256P-12 MB84256 mb84256-12ll HP121 M5M5256AP-70 M5M5256P M5M5256P-15 MB84256-10L
Contextual Info: 2 5 6 K £ tt £ ÌA&K& rc CMOS X A TAAC max ns) TCAC max (ns) TOE nax (ns) S t a t i c ^ y '/ TOH Bin (ns) TOD nax (ns) T»P «in (ns) RAM (3 2 7 6 8 x8 ) ft '•» TDS nin (ns) ffi TDH (ns) TWD ■in (ns) TWR nax (ns) LH52258-25 SHARP 0—70 25 25