LCC 18 PIN PACKAGE Search Results

QFJ018-P-R285-4

Contextual Info: PLASTIC LEADED CHIP CARRIER 18 PIN PLASTIC LCC-18P-M04 EIAJ code : ∗QFJ018-P-R285-4 Lead pitch 50mil Package width x package length 285 × 490mil Lead shape J bend Sealing method Plastic mold 18-pin plastic QFJ PLCC (LCC-18P-M04) 18-pin plastic QFJ (PLCC)

LCC 18 Pin Package

Abstract: QFJ018-P-R285-3 18pin Plastic QFJ LCC 16 Pin Package
Contextual Info: PLASTIC LEADED CHIP CARRIER FUJITSU SEMICONDUCTOR DATA SHEET 18 PIN PLASTIC To Top / Package Lineup / Package Index LCC-18P-M03 EIAJ code :∗QFJ018-P-R285-3 18-pin plastic QFJ PLCC Lead pitch 50 mil Package width x package length 285 × 425 mil Lead shape

Contextual Info: AS4C1259 883C 256K X 1 DRAM AUSTIN SEM IC O N D U C TO R , INC. « p DRAM 256K x 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883 18-Pin LCC 16-Pin DIP (D-2) FEATURES • Industry standard pinout and timing

Contextual Info: a 28-Leadless LCC Package E-28A Dimensions shown in inches and (mm) 0.100 (2.54)1 0.064 (1.63) 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) REF 26 25 18 19 0.458 (11.63) 0.442 (11.23) SQ 28 0.050 ±0.005 (1.27 ±0.13) 0.028 (0.71) 0.022 (0.56) 1 NO 1 PIN INDEX

Contextual Info: SCOPE: CMOS, 12-Bit Multiplying D/A Converter Device Type: -01 -02 Generic Number: MX7541S x /883B MX7541T(x)/883B Case Outline(s). Outline Letter Q E Mil-Std-1835 GDIP1-T18 or CDIP2-T18 CQCC1-N20 Case Outline Package Code 18 Lead CERDIP J18 20-Pin Ceramic LCC L20

Contextual Info: 2N3700HR Hi-Rel 80 V, 1 A NPN transistor Datasheet - production data Features BVCEO 80 V IC max 1A HFE at 10 V - 150 mA >100 1 2 3 3 3 TO-18 4 1 1 2 2 LCC-3 UB Pin 4 in UB is connected to the metallic lid Figure 1. Internal schematic diagram • Hermetic packages

Contextual Info: 2N3700HR Hi-Rel 80 V, 1 A NPN transistor Datasheet - production data Features BVCEO 80 V IC max 1A HFE at 10 V - 150 mA >100 1 2 3 3 3 TO-18 4 1 1 2 2 LCC-3 UB Pin 4 in UB is connected to the metallic lid Figure 1. Internal schematic diagram • Hermetic packages

2N2907AUB

Contextual Info: 2N2907AHR Hi-Rel 60 V, 0.6 A PNP transistor Datasheet - production data Features Parameter Value BVCEO 60 V IC max 0.6 A HFE at 10 V - 150 mA > 100 1 2 3 TO-18 3 3 4 1 1 2 2 LCC-3 • Hermetic packages UB  ESCC and JANS qualified Pin 4 in UB is connected to the metallic lid.

520200107R

Abstract: 2N2907A1 2N2907AUB
Contextual Info: 2N2907AHR Hi-Rel 60 V, 0.6 A PNP transistor Datasheet - production data Features Parameter Value BVCEO 60 V IC max 0.6 A HFE at 10 V - 150 mA > 100 1 2 3 TO-18 3 3 4 1 1 2 2 LCC-3 • Hermetic packages UB • ESCC and JANS qualified Pin 4 in UB is connected to the metallic lid.

CY7C235A

Contextual Info: CY7C235A / CYPRESS • Features • C M O S for optim um speed/power • H igh speed — 18 ns address set-up — 12 n s clock to output • IK x 8 Registered PROM Slim , 3 00-m il, 24-pin p lastic or h er­ m etic D IP o r 28-pin LCC an d PLCC • SV ± 10% Vc c , com m ercial and

Contextual Info: Industrial INC. TM PA7024I PEEL Array Programmable Electrically Erasable Logic Array Features • Industrial Grade Specifications I High-Speed, Moderate Power Consumption - Vcc = 4.5V to 5.5V, TA = -40°C to +85°C - Reprogrammable 24-pin DIP, SOIC, and 28-pin PLCC packages

Contextual Info: SCOPE: CMOS 12-BIT MULTIPLYING D/A CONVERTER Device Type 01 02 03 Generic Number MX7521S x /883B MX7521T(x)/883B MX7521U(x)/883B Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows: Case Outline Package Code Outline Letter

THX 201

Abstract: EP610 "pin compatible" PA7540P-15 PA7540 PA7540S-15 GAL6002
Contextual Info: To find out if the package you need is available, contact Customer Service PA7540 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 24-pin DIP, SOIC and 28-pin PLCC packages - Optional JN package for 22V10 power/ground

THX 201

Abstract: PA7572 "Programmable Electrically Erasable Logic Array" loadable counter with timing diagram PA7572P-20 PA7572F-20
Contextual Info: PA7572 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features

Contextual Info: Commercial INC. TM PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features I CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC, and PLCC packages I High-Speed, Moderate Power Consumption - As fast as 9ns/15ns tpdi/tpdx , 76.9MHz fmax

X 0404

Abstract: VSOR2000S1 M1005 SOIC-16 mpd dfn LCC16 MM4000 WOMC
Contextual Info: Tape and Reel Specifications Vishay Thin Film 8 mm, 12 mm, 16 mm and 24 mm Embossed Conductive Tape Conforming to EIA-481 Note • Chip resistor quantities less than 1000 pieces are typically packaged in bulk or waffle packs unless specified at time of order entry.

ICT Peel

Abstract: PA7572
Contextual Info: Commercial/Industrial PA7572 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP, 44-pin PLCC and TQFP packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features

Contextual Info: Commercial/ Industrial INC. TM PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features • CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC, and PLCC packages I Versatile Logic Array Architecture - 12 l/Os, 14 inputs, 36 registers/latches

TLO 81

Abstract: 16009A ICT Peel 26V12 PA7536 ma706
Contextual Info: Commercial/Industrial PA7536 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC and PLCC packages Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches

Contextual Info: SCOPE: CMOS 10-BIT MULTIPLYING D/A CONVERTER Device Type 01 02 03 Generic Number MX7520S x /883B MX7520T(x)/883B MX7520U(x)/883B Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows: Case Outline Package Code Outline Letter

Contextual Info: ADC-674 ® 12-Bit, P-Compatible A/D Converter PRODUCT OVERVIEW PRO The ADC-674 A/D converters are available in Th both cceramic leadless chip carrier and industry standa standard DIP packages. Th These units include a reference, clock, threestate ooutputs, and digital interface circuit which

QP7C261-25LI

Abstract: GDFP2-F24 5962-9080307MJA QP7C261 CQCC1-N28 QP7C261-35QMB 5962-9080306MLA QP7C263-25JC QP7C264 QP7C261-25WMB
Contextual Info: QP7C261 / QP7C263 / QP7C264 May 4, 2011 8K x 8 Power-Switched and Reprogrammable PROM Features • 5V ±10% VCC, commercial, industrial and military • Windowed Packages available for reprogrammability • OTP One-Time-Programmable Packages available • High speed

Am27C020

Contextual Info: Adva nce In fo rm a tio n a Am27C020 Advanced Micro Devices 2 MBil 256K x 8 CMOS EPROM DISTINCTIVE CHARACTERISTICS Compact 32-pin DIP package requires no hardwire change for upgrades to 8 Mbit High-performance CMOS technology Fast access time -1 0 0 ns Flaehrlte programming

QP7C261

Abstract: QP7C261-55WMB QP7C261-25WMB QP7C264 QP7C263 QP7C261-25WMB package 7C261 QP7C263-20JC QP7C261-35QMB GDFP2-F24
Contextual Info: QP7C261 / QP7C263 / QP7C264 October 9, 2007 8K x 8 Power-Switched and Reprogrammable PROM Features • 5V ±10% VCC, commercial, industrial and military • Windowed Packages available for reprogrammability • OTP One-Time-Programmable Packages available