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    LATTICE PACKAGE DIMENSION Search Results

    LATTICE PACKAGE DIMENSION Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    54ACT825/QKA
    Rochester Electronics LLC 54ACT825/QKA - Dual marked (5962-9161101MKA), D-Type Flip-Flop, 5V, 24-CFP PDF Buy
    TPH1R306PL
    Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 100 A, 0.00134 Ω@10 V, SOP Advance / SOP Advance(N) Datasheet
    TPH9R00CQH
    Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N) Datasheet
    TPH9R00CQ5
    Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 150 V, 64 A, 0.009 Ω@10 V, High-speed diode, SOP Advance / SOP Advance(N) Datasheet
    TPHR8504PL
    Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 40 V, 150 A, 0.00085 Ω@10 V, SOP Advance / SOP Advance(N) Datasheet

    LATTICE PACKAGE DIMENSION Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    JESD22-A108-A

    Abstract: JESD22-A104-A JESD22*108 EIA-671 JEDS22-C101-A doc-70 ISO14000 J-STD-035 8110014 Distributors and Sales Partners
    Contextual Info: Reliability and Quality Assurance February 2002 Introduction Lattice Semiconductor Corporation LSC designs, develops and markets high performance programmable logic devices (PLDs) and related development system software. Lattice Semiconductor is the inventor and world's leading supplier of in-system programmable (ISPtm) CPLDs. PLDs are standard semiconductor components that can


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    MIL-STD-883, MIL-STD-883E, J-STD-035 JESD22-A108-A JESD22-A104-A JESD22*108 EIA-671 JEDS22-C101-A doc-70 ISO14000 J-STD-035 8110014 Distributors and Sales Partners PDF

    ne 5555 timer

    Abstract: "Single-Port RAM"
    Contextual Info: ispLSI 6192 Cell-Based PLDs Cell-Based PLDs: The Wave of the Future! “ ” .Clearly the Next Wave of PLDs. T H IG H M I E IL T B S A Y M -S M IN RA G O R P M ER E FO M O RM R Y A P N C E Rhondalee Rohleder Pace Technologies R R LO EG G IST IC E T S


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    wave0260 I0071 ne 5555 timer "Single-Port RAM" PDF

    LCMXO1200

    Abstract: LCMXO2280 LCMXO256 LCMXO640 LVCMOS15 LVCMOS25 LVCMOS33 LCMXO1200C-3B256C package dimension 256-FTBGA vhdl code for 4 bit ripple carry adder
    Contextual Info: MachXO Family Handbook HB1002 Version 02.5, December 2010 MachXO Family Handbook Table of Contents December 2010 Section I. MachXO Family Data Sheet Introduction Features . 1-1


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    HB1002 TN1091 TN1086 TN1089 TN1092 LCMXO1200 LCMXO2280 LCMXO256 LCMXO640 LVCMOS15 LVCMOS25 LVCMOS33 LCMXO1200C-3B256C package dimension 256-FTBGA vhdl code for 4 bit ripple carry adder PDF

    Contextual Info: Lattice p L S r 1016 programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s pLSI Family — High-Speed Global Interconnects — 32 I/O Pins, Four Dedicated Inputs


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    pLS11016 1016-90LJ 44-Pin 1016-80LJ 1016-60LJI PDF

    Contextual Info: LATTICE SEMICONDUCTOR 4bE D il a t t ir p mL a C l « l i I w • SBfibTHT OÜOlMûb S ■ LAT pLSr 1024 w program m able Large Scale Integration : : : : T - v é - z i- ô « ? — Functional Block? Diagram* ¿m □ • PROGRAMMABLE HIGH DENSITY LOGIC — Member of Lattice’s pLSI Family


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    68-Pin T-fO-20 PDF

    transistor pt36c

    Abstract: pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962
    Contextual Info: Data Addendum March 2002 ORCA OR3LxxxB Series Field-Programmable Gate Arrays Introduction • ■ Features ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.25 µm 5-level metal technology. 2.5 V internal supply voltage and 3.3 V I/O supply


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    16-bit OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB1 OR3L225B7BM680I-DB1 DA99-011FPGA DA99-008FPGA DS99-087FPGA) transistor pt36c pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962 PDF

    Contextual Info: I Lattirp mmm \ J pLsr 1024 w Droarammable Intearation programmable Larae Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram □ • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family


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    pLS11024 1024-90LJ 68-Pin 1024-80LJ 1024-60LJ 1024-60LJI 1024-60LH/883 PDF

    Contextual Info: L a tti pp \J pLS11016 Droarammable Intearation programmable Larae Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — Member of Lattice's pLSI Family High-Speed Global Interconnects


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    pLS11016 1016-110LJ 44-Pin 1016-90LJ 1016-80LJ 1016-60LJ PDF

    Contextual Info: APR 2 2 19» Lattirp H I pLS11048 m# Droarammable Intearation programmable LaraeScale Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC Tm Member of Lattice’s pLSI Family High-Speed Global Interconnects


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    pLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ 1048-50LQI PDF

    Contextual Info: APR 2 2 1993 ispLSÎ 1024 in-system programmable Large Scale Integration High-Density Programmable Logic Features _ B Functional Block Diagram • IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — — Member of Lattice’s ispLSI Family


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    68-Pin ispLS11024 1024-90LJ 1024-80LJ 1024-60LJ PDF

    Contextual Info: I ha ftir p C I H I w !L is p L S 1 1 0 3 2 in-system programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s ispLSI Family — Fully Compatible with Lattice's pLSP Family


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    ispLS11032 1032-90LJ 84-Pin 1032-90LT 100-Pin 1032-80LJ ispLS11032-80LT 1032-60LJ PDF

    DS1016

    Abstract: UES23 ds1016-01
    Contextual Info: ispPAC-POWR6AT6 In-System Programmable Power Supply Monitoring and Margining Controller December 2008 Data Sheet DS1016 Application Block Diagram Features • Power Supply Margin and Trim Functions Trim and margin up to six power supplies Dynamic voltage control through I2C


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    DS1016 10-bit 32-Pin 1-800-LATTICE 3A-08. DS1016 UES23 ds1016-01 PDF

    Contextual Info: Lattice T'Aie Lattice ispLSI and pLSI 2000 Family ï i I Corporation Features_ J Introduction to ispLSI and pLSI 2000 Family ispLSI and pLSI 2000 Family □ 154 M Hz System Perform ance □ 5.5 ns Pin-to-Pin Delay □ High Density 1,000-6,000 PLD Gates


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    160-Pin 0212-80Bisp/2128 00413A 2128-100LM 2128-80LM PDF

    AL048

    Contextual Info: 4bE D LATTICE SEMICON DUC TOR iiiLattice m SaôbTMS 0001434 a B ILAT p L S r 1032 programmable Large Scale Integration _ Pft'-/Ÿ-OŸ •■■■■■ m mfn • PROGRAMMABLE HIGH DENSITY LOGIC I — fmax = 80 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay


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    135mA 44-Pin 68-Pin AL048 PDF

    EXO 32K

    Abstract: OR2C06A OR2C12A OR2T15B OR2T40B
    Contextual Info: Data Sheet November 2006 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology


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    16-bit 32-bit DS99-094FPGA DS98-022FPGA) EXO 32K OR2C06A OR2C12A OR2T15B OR2T40B PDF

    8B10B

    Abstract: ORT4622 PT10 PT11 STS-48 4032 k30 diode k30 4032 ASB27
    Contextual Info: Preliminary Data Sheet October 2003 ORCA ORT4622 Field-Programmable System Chip FPSC Four-Channel x 622 Mbits/s Backplane Transceiver Introduction Lattice has developed a solution for designers who need the many advantages of FPGA-based design


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    ORT4622 ORT4622 ORT4622BC432-DB 8B10B PT10 PT11 STS-48 4032 k30 diode k30 4032 ASB27 PDF

    00XXX001

    Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
    Contextual Info: Data Sheet November 2006 ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Baseline FPGA family used in Series 3+ FPSCs field programmable system chips which combine FPGA logic


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    OR3T20 OR3T30 1A-06. OR3T80 00XXX001 BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12 PDF

    AN6027

    Abstract: AN6026 151m75
    Contextual Info: In-System Programmable Analog Circuit October 2002 Data Sheet Features Functional Block Diagram • Flexible Interface and Programming Control • • • • Full configuration capability, SPI or JTAG modes Unlimited device updates using SRAM register E2CMOS for non-volatile configuration storage


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    15MHz 50kHz 600kHz) ispPAC30 28-Pin 24-Pin AN6027 AN6026 151m75 PDF

    PL1A

    Abstract: PLC water heater plc pin diagram 25032 PT15D b9 39a data sheet PL1C PT8C OR2C12A OR2T15B OR2T40B
    Contextual Info: Data Sheet January 2003 ORCA Series 2 Field-Programmable Gate Arrays Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, low-power 0.35 µm CMOS technology OR2CxxA , 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology


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    16-bit 32-bit DS99-094FPGA DS98-022FPGA) PL1A PLC water heater plc pin diagram 25032 PT15D b9 39a data sheet PL1C PT8C OR2C12A OR2T15B OR2T40B PDF

    R9C16

    Abstract: OR3T55 OR3TP12 PT10 PT11 PT12 PT13 PT14 PT15 PT16
    Contextual Info: Data Sheet October 2003 ORCA OR3TP12 Field-Programmable System Chip FPSC Embedded Master/Target PCI Interface Introduction Table 1. PCI Local Bus Data Rates Lattice has developed a solution for designers who need the many advantages of an FPGA-based design implementation coupled with the high bandwidth of the industry-standard PCI interface. The


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    OR3TP12 32-bit 64-bit. 32-/64-bit, 33/66MHz OR3T55 14x18 OR3TP12 OR3TP127BA256-DB OR3TP127BA352-DB R9C16 PT10 PT11 PT12 PT13 PT14 PT15 PT16 PDF

    Contextual Info: I atti P H l w !L i d P is p L S r 1 0 1 6 in-system programmable Large Scale Integration Features J Functional Block Diagram • in-system programmable HIGH DENSITY LOGIC — Member of Lattice’s IspLSI Family — Fully Compatible with Lattice's pLSI Family


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    44-Pin PDF

    Contextual Info: •■■ ■■a mm» p L S r 1016 Lattice programmable Large Scale Integration Functional Block Diagram Features • PROGRAMMABLE HIGH DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High Speed Global Interconnects 32 I/O Pins, Four Dedicated Inputs


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    pLS11016 44-Pin PDF

    Contextual Info: I attipp IL a C l H I U ispLSr 1032 in-systsm programmable Large Scale Integration Functional Block Diagram Features • In-system programmable HIGH DENSITY LOGIC — Member of Lattice's IspLSI Family — Fully Compatible with Lattice's pLSI Family — High Speed Global Interconnects


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    135mA ispLS11032 84-Pin PDF

    MACH4A

    Abstract: JTAG jtag mhz jtag 14 PQFP-144 ispLSI 2128-A M4A5-64 M5A3-384
    Contextual Info: 208-Ball BGA 256-Ball BGA 100-Ball BGA 49-Ball BGA 144-Ball BGA ® Fine Pitch BGA ispLSI, MACH, ispGDX & ispGAL Packages ® 7.00 x 7.00 mm 0.8 mm pitch 10.00 x 10.00 mm 0.8 mm pitch 13.00 x 13.00 mm 1.0 mm pitch 17.00 x 17.00 mm 1.0 mm pitch All dimensions refer to package body size


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    208-Ball 256-Ball 100-Ball 49-Ball 144-Ball 100-Pin 128-Pin 48-Pin 44-Pin 144-Pin MACH4A JTAG jtag mhz jtag 14 PQFP-144 ispLSI 2128-A M4A5-64 M5A3-384 PDF