LATTICE PACKAGE DIMENSION Search Results
LATTICE PACKAGE DIMENSION Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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54ACT825/QKA |
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54ACT825/QKA - Dual marked (5962-9161101MKA), D-Type Flip-Flop, 5V, 24-CFP |
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TPH1R306PL |
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N-ch MOSFET, 60 V, 100 A, 0.00134 Ω@10 V, SOP Advance / SOP Advance(N) | Datasheet | ||
TPH9R00CQH |
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MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N) | Datasheet | ||
TPH9R00CQ5 |
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N-ch MOSFET, 150 V, 64 A, 0.009 Ω@10 V, High-speed diode, SOP Advance / SOP Advance(N) | Datasheet | ||
TPHR8504PL |
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N-ch MOSFET, 40 V, 150 A, 0.00085 Ω@10 V, SOP Advance / SOP Advance(N) | Datasheet |
LATTICE PACKAGE DIMENSION Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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JESD22-A108-A
Abstract: JESD22-A104-A JESD22*108 EIA-671 JEDS22-C101-A doc-70 ISO14000 J-STD-035 8110014 Distributors and Sales Partners
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MIL-STD-883, MIL-STD-883E, J-STD-035 JESD22-A108-A JESD22-A104-A JESD22*108 EIA-671 JEDS22-C101-A doc-70 ISO14000 J-STD-035 8110014 Distributors and Sales Partners | |
ne 5555 timer
Abstract: "Single-Port RAM"
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wave0260 I0071 ne 5555 timer "Single-Port RAM" | |
LCMXO1200
Abstract: LCMXO2280 LCMXO256 LCMXO640 LVCMOS15 LVCMOS25 LVCMOS33 LCMXO1200C-3B256C package dimension 256-FTBGA vhdl code for 4 bit ripple carry adder
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HB1002 TN1091 TN1086 TN1089 TN1092 LCMXO1200 LCMXO2280 LCMXO256 LCMXO640 LVCMOS15 LVCMOS25 LVCMOS33 LCMXO1200C-3B256C package dimension 256-FTBGA vhdl code for 4 bit ripple carry adder | |
Contextual Info: Lattice p L S r 1016 programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s pLSI Family — High-Speed Global Interconnects — 32 I/O Pins, Four Dedicated Inputs |
OCR Scan |
pLS11016 1016-90LJ 44-Pin 1016-80LJ 1016-60LJI | |
Contextual Info: LATTICE SEMICONDUCTOR 4bE D il a t t ir p mL a C l « l i I w • SBfibTHT OÜOlMûb S ■ LAT pLSr 1024 w program m able Large Scale Integration : : : : T - v é - z i- ô « ? — Functional Block? Diagram* ¿m □ • PROGRAMMABLE HIGH DENSITY LOGIC — Member of Lattice’s pLSI Family |
OCR Scan |
68-Pin T-fO-20 | |
transistor pt36c
Abstract: pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962
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16-bit OR3L165B7BC432I-DB OR3L165B7BM680I-DB OR3L225B7BC432I-DB1 OR3L225B7BM680I-DB1 DA99-011FPGA DA99-008FPGA DS99-087FPGA) transistor pt36c pt36c PT35c transistor INTEL Core i5 760 PB7D pt35c k72 w5 OR3L165B8BM680-DB PB27A AL962 | |
Contextual Info: I Lattirp mmm \ J pLsr 1024 w Droarammable Intearation programmable Larae Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram □ • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family |
OCR Scan |
pLS11024 1024-90LJ 68-Pin 1024-80LJ 1024-60LJ 1024-60LJI 1024-60LH/883 | |
Contextual Info: L a tti pp \J pLS11016 Droarammable Intearation programmable Larae Large Scale Integration High-Density Programmable Logic Features Functional Block Diagram • PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — Member of Lattice's pLSI Family High-Speed Global Interconnects |
OCR Scan |
pLS11016 1016-110LJ 44-Pin 1016-90LJ 1016-80LJ 1016-60LJ | |
Contextual Info: APR 2 2 19» Lattirp H I pLS11048 m# Droarammable Intearation programmable LaraeScale Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features • PROGRAMMABLE HIGH-DENSITY LOGIC Tm Member of Lattice’s pLSI Family High-Speed Global Interconnects |
OCR Scan |
pLS11048 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ 1048-50LQI | |
Contextual Info: APR 2 2 1993 ispLSÎ 1024 in-system programmable Large Scale Integration High-Density Programmable Logic Features _ B Functional Block Diagram • IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — — — — — — Member of Lattice’s ispLSI Family |
OCR Scan |
68-Pin ispLS11024 1024-90LJ 1024-80LJ 1024-60LJ | |
Contextual Info: I ha ftir p C I H I w !L is p L S 1 1 0 3 2 in-system programmable Large Scale Integration High-Density Programmable Logic Functional Block Diagram Features IN-SYSTEM PROGRAMMABLE HIGH-DENSITY LOGIC — Member of Lattice’s ispLSI Family — Fully Compatible with Lattice's pLSP Family |
OCR Scan |
ispLS11032 1032-90LJ 84-Pin 1032-90LT 100-Pin 1032-80LJ ispLS11032-80LT 1032-60LJ | |
DS1016
Abstract: UES23 ds1016-01
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DS1016 10-bit 32-Pin 1-800-LATTICE 3A-08. DS1016 UES23 ds1016-01 | |
Contextual Info: Lattice T'Aie Lattice ispLSI and pLSI 2000 Family ï i I Corporation Features_ J Introduction to ispLSI and pLSI 2000 Family ispLSI and pLSI 2000 Family □ 154 M Hz System Perform ance □ 5.5 ns Pin-to-Pin Delay □ High Density 1,000-6,000 PLD Gates |
OCR Scan |
160-Pin 0212-80Bisp/2128 00413A 2128-100LM 2128-80LM | |
AL048Contextual Info: 4bE D LATTICE SEMICON DUC TOR iiiLattice m SaôbTMS 0001434 a B ILAT p L S r 1032 programmable Large Scale Integration _ Pft'-/Ÿ-OŸ •■■■■■ m mfn • PROGRAMMABLE HIGH DENSITY LOGIC I — fmax = 80 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay |
OCR Scan |
135mA 44-Pin 68-Pin AL048 | |
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EXO 32K
Abstract: OR2C06A OR2C12A OR2T15B OR2T40B
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16-bit 32-bit DS99-094FPGA DS98-022FPGA) EXO 32K OR2C06A OR2C12A OR2T15B OR2T40B | |
8B10B
Abstract: ORT4622 PT10 PT11 STS-48 4032 k30 diode k30 4032 ASB27
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ORT4622 ORT4622 ORT4622BC432-DB 8B10B PT10 PT11 STS-48 4032 k30 diode k30 4032 ASB27 | |
00XXX001
Abstract: BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12
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OR3T20 OR3T30 1A-06. OR3T80 00XXX001 BA 5979 R15C3 OR3T125 OR3T20 OR3T30 OR3T55 PT10 PT11 PT12 | |
AN6027
Abstract: AN6026 151m75
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15MHz 50kHz 600kHz) ispPAC30 28-Pin 24-Pin AN6027 AN6026 151m75 | |
PL1A
Abstract: PLC water heater plc pin diagram 25032 PT15D b9 39a data sheet PL1C PT8C OR2C12A OR2T15B OR2T40B
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16-bit 32-bit DS99-094FPGA DS98-022FPGA) PL1A PLC water heater plc pin diagram 25032 PT15D b9 39a data sheet PL1C PT8C OR2C12A OR2T15B OR2T40B | |
R9C16
Abstract: OR3T55 OR3TP12 PT10 PT11 PT12 PT13 PT14 PT15 PT16
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OR3TP12 32-bit 64-bit. 32-/64-bit, 33/66MHz OR3T55 14x18 OR3TP12 OR3TP127BA256-DB OR3TP127BA352-DB R9C16 PT10 PT11 PT12 PT13 PT14 PT15 PT16 | |
Contextual Info: I atti P H l w !L i d P is p L S r 1 0 1 6 in-system programmable Large Scale Integration Features J Functional Block Diagram • in-system programmable HIGH DENSITY LOGIC — Member of Lattice’s IspLSI Family — Fully Compatible with Lattice's pLSI Family |
OCR Scan |
44-Pin | |
Contextual Info: •■■ ■■a mm» p L S r 1016 Lattice programmable Large Scale Integration Functional Block Diagram Features • PROGRAMMABLE HIGH DENSITY LOGIC — — — — — Member of Lattice’s pLSI Family High Speed Global Interconnects 32 I/O Pins, Four Dedicated Inputs |
OCR Scan |
pLS11016 44-Pin | |
Contextual Info: I attipp IL a C l H I U ispLSr 1032 in-systsm programmable Large Scale Integration Functional Block Diagram Features • In-system programmable HIGH DENSITY LOGIC — Member of Lattice's IspLSI Family — Fully Compatible with Lattice's pLSI Family — High Speed Global Interconnects |
OCR Scan |
135mA ispLS11032 84-Pin | |
MACH4A
Abstract: JTAG jtag mhz jtag 14 PQFP-144 ispLSI 2128-A M4A5-64 M5A3-384
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208-Ball 256-Ball 100-Ball 49-Ball 144-Ball 100-Pin 128-Pin 48-Pin 44-Pin 144-Pin MACH4A JTAG jtag mhz jtag 14 PQFP-144 ispLSI 2128-A M4A5-64 M5A3-384 |