LAD2 5V Search Results

LAD1 5V

Abstract: LAD1 12v IT8761E IN4001 GPIO20 CLK48 GPIO14 IT8701F GPIO-12 LAD2 12V
Contextual Info: 8 7 6 5 4 3 2 1 IT8761E,FDC & COM D D SH1 C C B B REVISION HISTORY SCHEMATICS PCB DATE REVISION MODIFICATION ITEM DRAWING AND P.C.B. MODIFICATION DESCRIPTION REVISION ITSA-CG-99602 VER 0.2 JULY 07,99 Subject : IT8701F APPLICATION CIRCUIT. FIRST DRAFT A A ITE

7x7x1.4

Abstract: LPC47N217N GP10 PC99 SMSC LPC lpc interface
Contextual Info: LPC47N217N 64-Pin Super I/O with LPC Interface PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (14) Two IRQ Input Pins XNOR Chain

NS16C550

Abstract: 16C550 82077AA GP10 LPC47N267 LPC47N267-MN PC99
Contextual Info: LPC47N267 100 Pin LPC Super I/O with X-Bus Interface PRODUCT FEATURES „ „ „ „ „ „ 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (29) Four IRQ Input Pins X-Bus Interface — — —

80960KA

Abstract: 80960KB 80960MC 270775
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

SMSC LPC47N227

Abstract: 16C550 82077AA GP10 LPC47N227 LPC47N227-MT LPC47N227-MV NS16C550 PC99
Contextual Info: LPC47N227 100 Pin Super I/O with LPC Interface for Notebook Applications FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ 3.3 Volt Operation 5V Tolerant PC99 and ACPI 1.0b Compliant Programmable Wakeup Event Interface (nIO_PME Pin) SMI Support (nIO_SMI Pin) GPIOs (29)

MSI MS-5

Abstract: sony sd card ISO-7816 W83L518D multimedia card reader pin config intel 8086 assembly language CR GP11
Contextual Info: Winbond Integrated Media Reader W83L518D Datasheet W83L518D Data Sheet Revision History Pages 1 Dates Version 02/Jul. 1.0 Version Main Contents on Web 1.0 1st Release 2 3 4 5 6 7 8 Please note that all data and specifications are subject to change without notice. All the

fad27

Abstract: FAD47 FRQ01 FAD21 FAD30 FAD45 FAD26 fca 173 FAD 203 FAD37
Contextual Info: NEUBRIDGE MICROSYSTEMS NEWBRIDGE fc.4E D • b5öölQl JANUARY, 1993 MICROSYSTEMS Fully compatible with IEEE Std 896.1 - 1991 - Profiles A & B register selectable TTL input/output levels Low power CMOS implementation Futurebus+ interface - 896.1 compelled mode data transfer protocol

Contextual Info: 5hE D • M fl2bl7S INTEL 011M07S CORP 402 ■ IT L 1 U P/PR PH LS 80960KA EMBEDDED 32-BIT PROCESSOR ■ Built-In Interrupt Controller — 32 Priority Levels 256 Vectors — 3.4 jlis Latency @ 25 MHz _ Easy to Use, High Bandwidth 32-Bit Bus — 66.7 Mbytes/s Burst

Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military On-Chip Memory Management Unit — 4 Gigabyte Virtual Address Space per Task — 4 Kbyte Pages with Supervisor/User Protection High-Performance Embedded

a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

8BA22

Abstract: header 20X2 PCICON62B ba21 PCI9050 LA10 LA12 LA15 LA16 LA17
Contextual Info: A B C D E 2 CLK 2 PAR 2 IDSEL C/BE0# C/BE1# C/BE2# C/BE3# 2 RST# 2 INTA# 2 STOP# 2 PERR# 2 SERR# 2 FRAME# 2 DEVSEL# 2 IRDY# 2 TRDY# 2 LOCK# 2 2 2 2 2 AD[31.0] E 5V E 1 5 8 4 1 R2 2 2 10k R1 10k PE PRE CS SK DI GND VCC DO U3 93CS46 1 2 JUMPER JP3 5V 6 7 1

pin diagram of LED dot matrix display

Abstract: DOT matrix LED display full 28 pin DOT MATRIX led 5 x 7 dot matrix display 8 x 8 DOT MATRIX DISPLAY driver DOT matrix LED display p10 5X8 LED DOT MATRIX DISPLAY
Contextual Info: Part Number: www.SunLED.com MMDK60/IC 5X8 DOT MATRIX SERIAL INPUT DOT ADDRESSABLE INTELLIGENT DISPLAY DEVICES PRELIMINARY SPEC Dimensions in millimeters inch . Features 4 DIGITS, 5*8 DOT MATRIX. 8 BITS SERIAL DATA INPUT REGISTER AND LATCH REGISTER. 10*14 BITS STATIC RAM.

7 digit 7 segment lcd display

Abstract: 8031 microprocessor pin diagram of LED dot matrix display intel 8031 Set of Register intel 8031 instruction set intel 8031 gray code ic with number 8031 Intel Microprocessor 8 x 8 DOT MATRIX DISPLAY LED multiplexor driver
Contextual Info: Part Number: www.SunLED.com MSGK60/IC 5X8 DOT MATRIX SERIAL INPUT DOT ADDRESSABLE INTELLIGENT DISPLAY DEVICES Notes: 1. All dimensions are in millimeters inches . 2. Tolerance is ± 0.25(0.01") unless otherwise noted. Features 4 DIGITS, 5*8 DOT MATRIX. 8 BITS SERIAL DATA INPUT REGISTER AND LATCH REGISTER.

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

NS16550D

Abstract: f81216dg F81216 notes on serial communication DB9 IR 028p F81216D 30H22 LPC uart 0x61
Contextual Info: F81216 F81216D/DG LPC to 4 UART Datasheet Release Date: August, 2007 Version: V0.32P F81216. August, 2007 V0.32P F81216 F81216 Datasheet Revision History Version Date 0.22P 2003/07/22 0.23P 2003/07/31 Page 14 Revision History Updated WDT enable timer as power-on setting

cd 1619 CP AUDIO

Abstract: s48c CLEVO SIS-630S c319c PS2032 MF3 IC D41 sam AA121SJ03 z326 IC601
Contextual Info: s ß u j M B j Q o j e u i e i | o 0 FREQUENCY BSEL1 R 14 3 .a m . “ GTT H srr VREF VREF VREF VREF VREF VREF VREF VREF VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT/CPUVCC

TA80960KB

Abstract: 2T818 tl741
Contextual Info: intJ 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

218-0697020

Abstract: 218-0697014 SB820M IGP reflow profile southbridge block diagram 218-0697 sb850 sb700 SB820M reflow 605-FCBGA
Contextual Info: AMD SB820M Southbridge Databook Publication # Issue Date: 47283 Revision: 2.10 Dec 2010 Advanced Micro Devices 47283 Rev. 2.10 Dec 2010 AMD SB820M Southbridge Databook 2010 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced

218-0697020

Abstract: bcm50610 AMD Phenom II southbridge block diagram AMD Phenom II x4 218-0697014 pin diagram AMD phenom II - X4 SB820M BROADCOM AC131 605-FCBGA
Contextual Info: AMD SB810/850 Southbridge Databook Publication # Issue Date: 44758 Revision: 2.10 Dec 2010 Advanced Micro Devices 44758 Rev. 2.10 Dec 2010 AMD SB810/850 Southbridge Databook 2010 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced

MCS-8051

Abstract: MCS8051 W83L951DG W83L951D MKC2 6818 RTC pwm fan speed control 8051 Schematic diagram W83L951DG W83L951FG NEC protocol
Contextual Info: Winbond Mobile Keyboard and Embedded Controller W83L951DG W83L951FG Date: August/2006 Revision: 1.00 W83L951DG/W83L951FG W83L951DG/W83L951FG Data Sheet Revision History 1 PAGES DATES VERSION WEB VERSION n.a. 8/7/2006 1.0 1.0 MAIN CONTENTS First Release 2 3

IT8700F

Abstract: mtrb base B8H 16C550 MPU-401 PC99 lpc 935 ac motor control 946 motherboard
Contextual Info: IT8700F Simple Low Pin Count Input / Output Simple LPC I/O Preliminary Specification V0.1 Copyright  2001 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related

Contextual Info: XR28V382 3.3V DUAL LPC UART WITH 128-BYTE FIFO NOVEMBER 2013 REV. 1.0.0 GENERAL DESCRIPTION FEATURES The XR28V382 V382 is a dual Universal Asynchronous Receiver and Transmitter (UART) for the Intel Low Pin Count (LPC) bus interface. This device can replace or supplement a Super I/O device

Contextual Info: Ä G S M A N G E O M [F iG M T D @ të 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY Military • On-Chip Memory Management Unit — 4 Gigabyte Linear Address Space per Task — 4 Kbyte Pages with Supervisor/User

Contextual Info: REVISIONS LTR DESCRIPTION A B C D E F G DATE YR-MO-DA APPROVED 93-06-15 94-04-18 95-03-25 95-06-08 99-11-15 05-04-13 13-04-24 M. L. Poelking M. L. Poelking M. L. Poelking Thomas M. Hess M. L. Poelking Thomas M. Hess Thomas M. Hess Changes in accordance with NOR 5962-R144-93