LAD1 5V Search Results

NEC CIR

Abstract: PC XT MOTHERBOARD GP10 SIO1049 SIO1049-JV desktop MOTHERBOARD CIRCUIT diagram SERIRQ microsoft IR receiver
Contextual Info: SIO1049 LPC Media Center Consumer IR Controller with Windows VistaTM Remote Control Support PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V Tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin)

7x7x1.4

Abstract: NEC CIR rc5 protocol lad2 5v GP10 PC99 SIO1049 SIO1049-JV LAD010
Contextual Info: SIO1049 Super I/O with LPC Interface, with IrDA and Microsoft Windows® MCE Consumer IR Support PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V Tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin)

LAD1 5V

Abstract: LAD1 12v IT8761E IN4001 GPIO20 CLK48 GPIO14 IT8701F GPIO-12 LAD2 12V
Contextual Info: 8 7 6 5 4 3 2 1 IT8761E,FDC & COM D D SH1 C C B B REVISION HISTORY SCHEMATICS PCB DATE REVISION MODIFICATION ITEM DRAWING AND P.C.B. MODIFICATION DESCRIPTION REVISION ITSA-CG-99602 VER 0.2 JULY 07,99 Subject : IT8701F APPLICATION CIRCUIT. FIRST DRAFT A A ITE

GP54 diode

Abstract: LAD1 12v lad1 5v 8P4R 4.7k DIODE GP25 WPT 95 12 ps2ms IT8711F DIODE GP54 GP50
Contextual Info: 5 D 4 3 2 1 D IT8711F Application Circuit V0.2 Page1 : Revision History Page2 : IT8711F Page3 : Serial & Parallel Ports Page4 : VID,IR,CIR,FDC & Smart Card Reader Connector Page5 : Layout & Routing Guideline C C REVISION HISTORY SCHEMATIC REVISION PCB REVISION

Contextual Info: LPC47N217 64-Pin Super I/O with LPC Interface Data Brief Product Features ƒ 3.3 Volt Operation 5V tolerant ƒ Multi-Mode Parallel Port with ChiProtect − Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port − Enhanced Parallel Port (EPP) Compatible - EPP 1.7

MO-36-QFN-6x6

Abstract: sio1036 lpc interface MO-220 PC99 SIO1036 SIO1036-ZG
Contextual Info: SIO1036 Super I/O with LPC Interface with FIR and Consumer IR Support PRODUCT FEATURES „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V tolerant GPIOs (1) XNOR Chain PC99a, PC2001 36-pin QFN Lead-free RoHS Compliant Package Intelligent Auto Power Management

Contextual Info: SIO1036 Super I/O with LPC Interface with FIR and Consumer IR Support PRODUCT FEATURES „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V tolerant GPIOs (1) XNOR Chain PC99a, PC2001 36-pin QFN Lead-free RoHS Compliant Package Intelligent Auto Power Management

askir

Abstract: SIO1036-AEZG
Contextual Info: SIO1036 Super I/O with LPC Interface with FIR and Consumer IR Support PRODUCT FEATURES • ■ ■ ■ ■ ■ ■ Data Brief 3.3 Volt Operation 5V tolerant GPIOs (1) XNOR Chain PC99a, PC2001 36-pin QFN package, green, lead-free package also available Intelligent Auto Power Management

7x7x1.4

Abstract: LPC47N217N GP10 PC99 SMSC LPC lpc interface
Contextual Info: LPC47N217N 64-Pin Super I/O with LPC Interface PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (14) Two IRQ Input Pins XNOR Chain

MO-220 8x8

Abstract: LPC47N217 LPC47N217N-ABZJ-TR LAD1 5V GP10 LPC47N217N PC99 56-QFN
Contextual Info: LPC47N217N 56-Pin Super I/O with LPC Interface PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (13) Two IRQ Input Pins XNOR Chain

Contextual Info: SIO1000 Super I/O with LPC Interface with FIR and Consumer IR Support PRODUCT FEATURES ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ ̈ Data Brief 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (14) Two IRQ Input Pins

SIO1000

Abstract: GP10 PC99 SIO1000-JV
Contextual Info: SIO1000 Super I/O with LPC Interface with FIR and Consumer IR Support PRODUCT FEATURES „ „ „ „ „ „ „ „ „ „ „ Data Brief 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (14) Two IRQ Input Pins

GP25

Abstract: IT8706R
Contextual Info: IT8706R Special General Purpose I/O Preliminary Specification V0.1 Copyright  2000 ITE, Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products

80960KA

Abstract: 80960KB 80960MC TA80960KA pga 132 packaging
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

80960KA

Abstract: 80960KB 80960MC 270775
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

NS16C550

Abstract: LPC47N227-MN 16C550 82077AA LPC47N227 LPC47N227-MT LPC47N227TQFP PC99 SMSC LPC47N227
Contextual Info: LPC47N227 100 Pin Super I/O with LPC Interface for Notebook Applications FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ 3.3 Volt Operation 5V Tolerant PC99 and ACPI 1.0b Compliant Programmable Wakeup Event Interface (nIO_PME Pin) SMI Support (nIO_SMI Pin)

NS16C550

Abstract: 16C550 82077AA GP10 LPC47N267 LPC47N267-MN PC99
Contextual Info: LPC47N267 100 Pin LPC Super I/O with X-Bus Interface PRODUCT FEATURES „ „ „ „ „ „ 3.3 Volt Operation 5V tolerant Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (29) Four IRQ Input Pins X-Bus Interface — — —

SMSC LPC47N227

Abstract: 16C550 82077AA GP10 LPC47N227 LPC47N227-MT LPC47N227-MV NS16C550 PC99
Contextual Info: LPC47N227 100 Pin Super I/O with LPC Interface for Notebook Applications FEATURES ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ 3.3 Volt Operation 5V Tolerant PC99 and ACPI 1.0b Compliant Programmable Wakeup Event Interface (nIO_PME Pin) SMI Support (nIO_SMI Pin) GPIOs (29)

MSI MS-5

Abstract: sony sd card ISO-7816 W83L518D multimedia card reader pin config intel 8086 assembly language CR GP11
Contextual Info: Winbond Integrated Media Reader W83L518D Datasheet W83L518D Data Sheet Revision History Pages 1 Dates Version 02/Jul. 1.0 Version Main Contents on Web 1.0 1st Release 2 3 4 5 6 7 8 Please note that all data and specifications are subject to change without notice. All the

fad27

Abstract: FAD47 FRQ01 FAD21 FAD30 FAD45 FAD26 fca 173 FAD 203 FAD37
Contextual Info: NEUBRIDGE MICROSYSTEMS NEWBRIDGE fc.4E D • b5öölQl JANUARY, 1993 MICROSYSTEMS Fully compatible with IEEE Std 896.1 - 1991 - Profiles A & B register selectable TTL input/output levels Low power CMOS implementation Futurebus+ interface - 896.1 compelled mode data transfer protocol

a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

SW-SPDT-mom

Abstract: DEUTSCH connectors abc HD5X2 GA20 PC87364 PC99 infrared SWITCH CIRCUIT DIGRAM GPIO46 FDC11 ABC DEUTSCH connectors
Contextual Info: - February 1998 National Semiconductor Shai Altman December 1998 The PC87364, a member of National Semiconductor’s 128pin LPC SuperI/O family, introduces wake-up support for a wide range of wake-up events, and new hardware and software features to protect the system. The PC87364 provides

160-Pin Flat Package pci bridge

Contextual Info: 936&5HY$ PCI Bus Target Interface Data Sheet Revision 1.1 V3 Semiconductor Corp V3 Semiconductor makes no warranties for the use of its products. V3 does not assume any liability for errors which may appear in this document, however, we will attempt to notify customers of such errors.

AD29

Abstract: AD30 V350EPC V350EPC-33 V350EPC-40 V960PBC V961PBC V96BMC
Contextual Info: V350EPC Rev. A0 LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS • Glueless interface to Intel’s i960Jx and IBM’s PowerPCTM 401Gx processors • On-the-fly byte order endian conversion • I2O ATU and messaging unit including hardware controlled circular queues