L22V10 Search Results

TIBPAL22V

Contextual Info: P R O G R A M M A B L E LOGIC Introduction Texas Instruments Military Products is committed to meeting your system requirement needs for programmable logic. Tl offers a variety of programmable logic devices to help bridge the gap between S S I/ M S I and LSI/Gate A rrays in military designs. With a single PAL 1C from

Contextual Info: PRELIMINARY CYPRESS SEMICONDUCTOR • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 5 ns — tsu = 2.5 ns — fMAX= 153.8 MHz • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­ tional V cc and Vs s pins for lowest

22V10G-7

Contextual Info: m f CYPRESS Features — f[HAX = 1 6 6 MHz External • Reduced ground bounce and under­ shoot • PLCC and LCC packages w ith addi­ tional Vc c and V ss pins for lowest ground bounce • Up to 22 inputs and 10 outputs for more logic power Synchronous PRESET, asynchronous

Contextual Info: L22V10 Lattice High Performance E2CMOS PLD Generic Array Logic Semiconductor Corporation FEATURES FUNCTIONAL BLOCK DIAGRAM HIGH PERFORMANCE E2CMOS TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.5 ns Maximum from Clock Input to Data Output

am29203 "evaluation board"

Abstract: L0512 MV8000 TTL catalog CL1101 8038 ic tester circuit diagram tl 2345 ml gcr encoder parallel bus arbitration 30GRAMMABLE
Contextual Info: PROGRAMMABLE ’ROGRAMMABLE 30GRAMMABLE L DGRAMMABLE LG 3RAMMABLE LOG ÏRAMMABLE LOGI ÌAMMABLE LÄGIC a Advanced Micro Devices Programmable Array Logic Handbook Prepared by the Product Planning and Applications Staff at Advanced M icro Devices, Inc. Brad Kitson, Editor

GAL22V10-25LP

Abstract: GAL22V10-15LP GAL22V10-20LP gal22v10b15lpi GAL22V10-25LPI lattice 22v10 programming specification GAL22V10-20LPI GAL22V10B15LP GAL22V10B-15U GAL22V10-15L
Contextual Info: L22V10B L22V10 t i PC O :L d I IIÜ •■■■■■ FEATURES High Performance E2CMOS PLD F U N C T IO N A L B L O C K D IA G R A M • HIGH PERFORMANCE E’ CMOS» TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 105 MHz — 7 ns Maximum from Clock Input to Data Output

22V10G

Contextual Info: PRELIMINARY r0 CYPRESS • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpo = 4 ns — ts = 2.5 ns — fMAX = 166 M Hz External • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­ tional V cc and Vs s pins for lowest

P10CF-10PC

Contextual Info: L22V10CF _ PAL22VP10CF ^ SEMICONDUCTOR Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpo = 7.5 ns — t§u = 3 ns — fM AX — 2 new feedback paths PAL22VP10CF • Synchronous PRESET, asynchronous

Contextual Info: L22V10G PAL22VP10G PRELIMINARY ” I CYPRESS SEMICONDUCTOR • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpD = 5 ns — tgu = 2.5 ns — fMAX = 153.8 MHz • Reduced ground bounce and under­ shoot • PLCC and LCC packages with addi­

Contextual Info: LATTICE SEMICONDUCTOR böE » • SBÔb'îM'J □DDS'îlO TTb « L A T L22V10 Lattice In-System Program m able E2C M O S PLD Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • IN-SYSTEM PROGRAMMABLE 5-VONLY — 4-Wire Serial Programming Interface

GAL22V10-20LP

Abstract: GAL22V10-15LP gal22v10-15
Contextual Info: Lattice Semiconductor G A L 22 V 1 0B L22V10 Corporation High Performance E2CMOS PLD FUNCTIONAL BLOCK DIAGRAM FEATURES •HIGH PERFORMANCE E*CMOS* TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 105 MHz — 7 ns Maximum from Clock Input to Data Output

L22V10C-10PC

Contextual Info: L22V10C PAL22VP10C y CYPRESS Universal PAL Device B iC M O S process and Ti-W fuses, the L22V10C and PAL22VP10C use the fam iliarsum -of-products A N D -O R logic structure and a new concept, the program ­ m able m acrocell. • 10 user-programmable output

Contextual Info: L22V10/883 Lattice High Performance E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation Functional Block Diagram Features • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 1 6 6 MHz — 7ns Maximum from Clock Input to Data Output

ot 112

Abstract: 48-PIN EL101 h1213
Contextual Info: DENSE-PAC MICROSYS TE MS 2ñE D • 27ST41S 00Q1G17 S HIDPC L22V10A Dense-Pac Microsystems; Inc. PROGRAMMABLE LOGIC M ODULE D E SC R IP T IO N : The Dense-Pac Programmable Logic M odule DPL is a 48-pin Pin Grid Array (PGA) designed to support two "2 2 V 1 0 " field programmable array logic, 22 input, 10

gal20v10

Abstract: lattice 20v10 lattice 20v10 programming 7128SQC100-7 LT 7202 20v10 IDT722X1 PAL AM 16v8 "ITE Tech" modem mpix
Contextual Info: FIFO APPLICATIONS GUIDE September 1999 1 IDT maintains a home page on the World Wide Web. The URL is: www.idt.com. The most current information available regarding all IDT products, company information, and services can be accessed from the home page, which is updated daily. IDT also provides a CDROM containing the latest

PAL 002a

Abstract: PAL10020EG8 pal10h PAL10H20EV8
Contextual Info: a PALI 0H20EG8-6/PAL10020EG8-6 Advanced Micro Devices ECL Latched Programmable Array Logic DISTINCTIVE CHARACTERISTICS High-performance; tp o • 6 ns Eight user-programmable output logic macrocells for latched or combinatorial operation A registered version of the device is available as

Contextual Info: Lattice G A L 2 2 V 1 0 /8 8 3 High Performance E2CMOS PLD Generic Array Logic ; Semiconductor I Corporation FUNCTIO N AL B LO C K DIAGRAM FEATURES • HIGH PERFORMANCE E ^M O S TECHNOLOG Y — 10 ns Maxim um Propagation Delay — Fmax = 1 6 6 MHz — 7ns Maximum from Clock Input to Data O utput

L22V10

Abstract: AL22V10
Contextual Info: Lattice FEATURES G L22V10/883 High Performance E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM • HIGH PERFORMANCE E’ CMOS* TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax =166 MHz — 7ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs

gal16v8d

Abstract: GAL16V8-15L gal22v10d GAL20V8-15L P20V8B-15LP GAL16V8 15LP GAL16V8D-25QP GAL20V8B-15QP DIP-24 GAL16V8D-15QP
Contextual Info: MHTEPTEKC ww w.i-t.su ¡nfo@ i-t.su Ten: 495 739-09-95, 644-41-29 MMKpocxeMbi TMna GAL b Kopnyce DIP LATTICE n o MHflMBMAyanbHOMy 3aKa3y npeflnaraeM TaKwe flpyrw e MMKpocxeMbi TMna GAL $ npM bi LATTICE. Bonee noflpo6Han MH^opMauMn - b HameM OTflene npoflaw.

10DC IR 3 PINS

Contextual Info: L22V10C PAL22VP10C PRELIMINARY CYPRESS SEMICONDUCTOR Features • • — 10-ns tpu, 90-M H z, Tmax BiCMOS technology • lip to 22 inputs and 10 outputs for more logic power • • Variable product terms High reliability — Proven Ti-W fuse technology

ic 5304 smd 8 pin

Abstract: lattice 22v10 programming specification 5304 smd 8 pin ic 5304 smd GAL22V10 lattice 22v10 GAL22V10-25LR gal22v10b 5962-8984103LA al22v10
Contextual Info: 47E B LA T T I C E S E M I C O N D U C T O R • saabmi 0003112 S H L A T GAL22V1 OB/883 L22V10/883 iiiLattice High Perlcfmanc» gCMOS PLD -0 7 FUN CT IO N A L BLO C K D IAG RAM FEATURES • HIGH PERFORMANCE E^CMOS* TECHNOLOGY — 15 ns Maximum Propagation Delay

Contextual Info: International CMOS Technology Commercial/ Industrial PEEL 22CV10AZ-25 CMOS Programmable Electrically Erasable Logic Device Architectural Flexibility Features • - Ultra Low Power Operation - V cc = 5 Volts ±10% - Icc = 25 |iA typical at standby - Icc = 3.5 m A (typical) at 1 MHz

Square D 8501 PH 44 E

Contextual Info: PM I S tandard P r o d u c t I PM C-Sierra, Inc. 1^^ PMC-940106 ISSUE 3, May 16, 1994 P M 5 9 4 5 SAP I DAUGHTERBOARD PM5945 ATM S A P I SONET PHYSICAL INTERFACE BOARD S tandard P r o d u c t PMC-940106 ISSUE 3, May 16, 1994 PM I I 1^^™ PM C-Sierra, Inc.

Contextual Info: Lattice I• • L22V10 High Perform ance E2CM O S PLD G eneric A rray Logic J Semiconductor • Corporation FU N C TIO N AL B LO C K DIAGRAM FEATURES • HIGH PERFORMANCE E2CMOS TECHNOLOG Y — 5 ns Maxim um Propagation Delay — Fmax = 200 MHz — 4 ns Maxim um from Clock Input to Data Output