L*66 CL PE Search Results

Contextual Info: SO LI » S T A TE DEVICES 1EE INC D | ò3t.bD ll O O D l clñ4 1 | T - 0 . 3 ~ £>7 SHA395A thru SHA395C 12 AMP ULTRA FAST CENTERTAP RECTIFIER 100-200 VOLTS CASE STYLE P JEDEC TO-66 14830 Valley View Avenue La Mirada. California 90638 213 921-9660 TW X 910-583-4807

400J

Contextual Info: 3J/I92E Air-Blast-Cooled R.F. Triode 3J/I92E CATHODE. Thoriated tungsten filament Voltage Nom inal current Peak emission 5 66 12 V A A 17 1,500 Cl R A T IN G . Amplification factor J Measured at 'j Impedance \ Va 6kV, I a 0.9A J D IR E C T IN T E R - E L E C T R O D E C A P A C IT IE S .

CDC9841

Contextual Info: CDC9841 PC M O T H E R B O A R D C L O C K S Y N T H E S I Z E R / D R I V E R WITH 3-STATE O U T P U T S S C A S 458D - DECEMBER 1 9 9 4 - REVISED APRIL 1996 DW PACKAGE TOP VIEW * F ou r CPU Cl o c k O u t p u t s With Program ma ble Frequency (SO M H z , 60 M H z , and 66 M H z )

T01-104

Abstract: 41 Tube T01001 SPEC-0042
Contextual Info: 2006/05/22 BY SPEED TECH CORP. ALL RIGHTS RESERVED,PRODUCTS ARE COVERED BY PATENTS AND/OR PATENTS PENDING. / Lü > è Cd ca LÜ o_ CL <c £ OL LÜ . > > .0 C£ zip < 00 o I Z C£ I S .< L . o z q P O _O Q _Ü P I— Lü Lü Lü X _l < (/) I a: Qi Lü

Single Pedal

Abstract: F1-U1Z F1-U1Z R f1-u2zd
Contextual Info: Footswitches with single pedal F1 Protection class IP 65 Designation Part number Circuit diagram pressure point 1 F1-U1Z 606.1100.005 F1-U1Y 606.1100.001 F1-SU1Z 606.1300.011 23 23 24 21 22 12 13 14 11 24 12 11 F1-SU1 Mi RG 616.1300.327 P3 P1 P2 14 11 12

1505C

Abstract: 48MHZ CDC930 crystal 26 Mhz package 2 x 6
Contextual Info: SCAS641 – JULY 2000 Generates Clocks for Pentium 4 Microprocessors Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies Includes Spread Spectrum Clocking SSC , 0.6% Downspread for Reduced EMI With Theoretical EMI Damping of 7 dB† Power Management Control Terminals

Contextual Info: Semiconductor April 1992 DM54LS240/DM74LS240, DM54LS241/DM74LS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description These buffers/line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers/ drivers employed as memory-address drivers, clock drivers,

Contextual Info: SECON OAKY tMPEOJINCE OHMIS \ t S S rto tie s - PICO'S 77000 SERIES nco PART PRIMARY IM PEOANCi OHMS PO WER WATTS S P l IT WIND NOS 8ER PAR 1KHz 400 Hz m MflNr I SEC MDARY ISO Hz UNfeALANCEO DC CURRENT PRIMARY DC Hfhsr m RESISTANCE OHMS m UfiN f PRIMARY ic e

Contextual Info: CDC930 133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3ĆSTATE OUTPUTS SCAS641 − JULY 2000 D Generates Clocks for Pentium4 D D D D D D D D Microprocessors Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies

P123E05

Contextual Info: Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five lowskew outputs that are synchronized with the input. The

1505C

Abstract: 48MHZ CDC930
Contextual Info: CDC930 133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS641 – JULY 2000 D D D D D D D D D Generates Clocks for Pentium4 Microprocessors Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies Includes Spread Spectrum Clocking SSC ,

PL123E-05SC

Contextual Info: Preliminary PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION • • • • The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five lowskew outputs that are synchronized with the input. The

Contextual Info: Preliminary PL123E-05 Low Skew Zero Delay Buffer DESCRIPTION FEATURES The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to

Contextual Info: Preliminary PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to

1505C

Abstract: 48MHZ CDC930
Contextual Info: CDC930 133ĆMHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3ĆSTATE OUTPUTS SCAS641 − JULY 2000 D Generates Clocks for Pentium4 D D D D D D D D Microprocessors Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies

Contextual Info: S C IE N T IF IC / M IN I-C IR C U IT S 4 TE D • flQ b flflll DOD1 4 7 R 2 1 2 * S C C broadband, high dynamic range Frequ ncy Mix©rs # TUF-860MH LEV EL 13 +13 dBm LO, up to +9 dBm RF T -7 4 -0 9 -0 1 computer-automated perform ance data typical production unit

Contextual Info: Preliminary PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The sy nchronization is established via CLKOUT feed back to

P123E09H

Abstract: PL123E-09 PL123E-09HSC
Contextual Info: Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has two lowskew output banks, of 4 outputs each, that are synchronized with the input. Control of the two banks of

Contextual Info: Electrical Characteristics and Timing Electrical Specifications Symbol Value Unit < o o Table 7 Maximum Ratings GND = 0 Vdc Rating -0.3 to +7.0 V Vin GND - 0.5 to Vcc + 0.5 V Current Drain per Pin excluding VCc and GND I 10 mA Operating Temperature Range (5 volt devices)

IEC-947-5-1 ip 66

Contextual Info: Switches Footswitches with two pedals F2 Protection class IP 65 Designation Part number Circuit diagram F2-U1Z/U1Z 606.2110.013 F2-U2Z/U2Z 606.2220.015 23 24 23 24 43 44 43 44 11 12 11 12 31 32 31 32 23 24 23 24 11 12 11 12 l/– – – – – – – Slow make & break/snap action

ps 0800

Abstract: PL123E-09HSC-R PL123E-09HSC
Contextual Info: PL123E-09 Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has two low-skew output banks, of 4 outputs each, that are synchronized

PL123E-09HSC

Abstract: 16-Pin TSSOP theta Jc value PL123E-09 PL123E-09OC P123E-09 P123E09H
Contextual Info: PL123E-09 Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION • • • • The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has two lowskew output banks, of 4 outputs each, that are synchronized with the input. Control of the two banks of

XC7372

Contextual Info: HXILINX XC7372 72-Macrocell CMOS CPLD June 1 ,1 9 9 6 Version 1.0 Product Specification Features tion Blocks are turned off and unused m acrocells in used Function Blocks are configured for low power operation. • High-perform ance Com plex Program mable Logic

Contextual Info: PRELIMINARY PRELIM f f j PER!COM PI6C102 Precision Clock Synthesizer for Mobile PCs Features Description The PI6C102 is a high-speed low-noise clock generator