K 1413 Search Results

proton rx 4000 watts power amplifier circuit diagram

Abstract: Hamamatsu r300 0812E H5783
Contextual Info: PHOTOMULTIPLIER TUBES Basics and Applications THIRD EDITION Edition 3a PHOTON IS OUR BUSINESS 2007 HAMAMATSU PHOTONICS K. K. ▲ Photomultiplier Tubes ▲ Photomultiplier Tube Modules © 2007 HAMAMATSU PHOTONICS K. K. Introduction Light detection technolgy is a powerful tool that provides deeper understanding of more sophisticated

DM74LS109AN

Abstract: DM54LS109AW DM74LS109A DM74LS109AM J16A 54LS109 54LS109DMQB 54LS109FMQB DM54LS109AJ
Contextual Info: DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the

DM5473J

Abstract: DM5473W DM7473N 5473FMQB 5473DMQB DM7473 J14A N14A W14B
Contextual Info: DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock

DM74LS73AN

Abstract: DM74LS73A DS006372 DM54LS73AJ DM54LS73AW DM74LS73AM J14A M14A N14A W14B
Contextual Info: DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on

DM5476J

Abstract: DM7476 5476DMQB 5476FMQB DM5476W DM7476N J16A N16E W16A
Contextual Info: DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock

54LS112

Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN DM74LS112
Contextual Info: DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the

Contextual Info: mmnax PM400DVA060 Powerex, Inc., 200 Hillis Street, Youngwood, Pennsylvania 15697-1800 724 925-7272 //? t & llif T IO d M O C Iu IG Single Phase IGBT Inverter Output 400 Amperes/600 Volts ♦j K |* «| K |* *| K |* TERMINAL CODE 1. 2. 3. 4. 5. n Vnc

74LCX109MTC

Abstract: "J-K Flip flops" 74LCX109 74LCX109SJ 74LCX109SJX M16D Fairchild Semiconductor technology
Contextual Info: November 1996 74LCX109 Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX109 are dual J-K flip-flops. Each flip-flop has independent J, K , PRESET, CLEAR, and CLOCK inputs and Q, Q outputs. These devices are edge sensitive and change

5476DMQB

Abstract: 5476FMQB DM54 DM5476J DM5476W DM7476 DM7476N J16A N16E W16A
Contextual Info: S E M IC O N D U C T O R tm DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs General Description This device contains two independent positive pulse trig­ gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock

74LVX112

Abstract: 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
Contextual Info: 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The LVX112 is a dual J-K Flip-Flop where each flip-flop has independent inputs J, K, PRESET, CLEAR, and CLOCK and outputs (Q, Q). These devices are edge sensitive and change states synchronously on the negative going transition of the clock pulse. Triggering occurs at a voltage level of

rs 5493 data sheet

Abstract: transistor d 5702 e d 5703 T242D336K050 T222B105K075 T111C2 2748 marking 3021 std 5252 f 0917 CV 7311 CSR 6026
Contextual Info: TANTALUM HERMETICALLY SEALED / AXIAL — MIL-PRF-39003 ORDERING INFORMATION OBSOLETE* CSR XX B 565 K M TYPE FAILURE RATE LEVEL IN % PER 1000 HOURS Capacitors, Fixed, Solid Electrolyte, Tantalum Established Reliability GRADED A — Not Applicable B — 0.1%/k hrs.

5252 F 0911

Abstract: CSR 6026 s0112 military capacitor kemet t140 d 2060 M39003/10-3078S T110A104K075AS 5252 f 0916 on 5295 transistor
Contextual Info: TANTALUM HERMETICALLY SEALED / AXIAL — MIL-PRF-39003 ORDERING INFORMATION OBSOLETE* CSR XX B 565 K M TYPE FAILURE RATE LEVEL IN % PER 1000 HOURS Capacitors, Fixed, Solid Electrolyte, Tantalum Established Reliability GRADED A — Not Applicable B — 0.1%/k hrs.

5252 F 0918

Abstract: 5252 F 0911 CSR 6026 CSR09 2401 7318 5252 F 1003 7135 35v U 4076 CSR13 MIL-PRF-39003
Contextual Info: TANTALUM HERMETICALLY SEALED / AXIAL — MIL-PRF-39003 ORDERING INFORMATION OBSOLETE* CSR XX B 565 K M TYPE FAILURE RATE LEVEL IN % PER 1000 HOURS Capacitors, Fixed, Solid Electrolyte, Tantalum Established Reliability GRADED A — Not Applicable B — 0.1%/k hrs.

5252 F 0911

Abstract: M39003/10 5252 F 0910 CSR 6026 0741 8129 3139 147 1330 5252 0916 2322 7346 1006 4213 A 5252 f 0917
Contextual Info: TANTALUM HERMETICALLY SEALED / AXIAL — MIL-PRF-39003 ORDERING INFORMATION OBSOLETE* CSR XX B 565 K M TYPE FAILURE RATE LEVEL IN % PER 1000 HOURS Capacitors, Fixed, Solid Electrolyte, Tantalum Established Reliability GRADED A — Not Applicable B — 0.1%/k hrs.

5252 F 0911

Abstract: 5252 F 0921 5252 F 1104 CSR 6026 T213D CV 7311 0782 K 2564 TYPE CSR13 5252 F 1002 5252 F 1003
Contextual Info: KEMET TANTALUM HERMETICALLY SEALED / AXIAL — MIL-C-39003 ORDERING INFORMATION OBSOLETE* CSR XX B 565 K M TYPE FAILURE RATE LEVEL IN % PER 1000 HOURS Capacitors, Fixed, Solid Electrolyte, Tantalum Established Reliability GRADED A — Not Applicable B — 0.1%/k hrs.

74F113

Abstract: F113 M14A M14D N14A 74F113PC 74F113SC 74F113SJ
Contextual Info: 74F113 Dual JK Negative Edge-Triggered Flip-Flop Asynchronous input: General Description The ’F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be

995kHz

Contextual Info: 19-1413; Rev 0; 12/98 > k i y i x i > k i + 5 V Si ngl e- Suppl y, 1 M s p s , 16-Bit Self-Calibrating ADC The MAX1200 16-bit, monolithic, analog-to-digital con­ v e rte r AD C is c a p a b le of c o n v e rs io n rates up to 1Msps. This CMOS integrated circuit uses a fully differ­

5252 F 0911

Abstract: 5252 f 0917 KEMET T110 SERIES kem 5361 5252 F 0918 5252 F 0921 CSR 6026 5252 F 0910 5252 F 1004 2842 dc motor
Contextual Info: K E M E T TANTALUM HERMETICALLY SEALED / AXIAL — MIL-C-39003 ORDERING INFORMATION OBSOLETE * C S R X X B 5 6 5 K M TYPE FAILURE RATE LEVEL IN % PER 1000 HOURS Capacitors, Fixed, Solid Electrolyte, Tantalum Established Reliability GRADED A— Not Applicable

Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary

54LS112

Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN E20A
Contextual Info: S E M IC O N D U C T O R tm DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains tw o independent negative-edge-triggered J-K flip-flops w ith com plem entary

DM74S112

Abstract: DM54S112 DM54S112J DM74S112N J16A N16E
Contextual Info: DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is high or low without affecting the outputs as long as setup

mh7493

Abstract: MA0403A maa 502 MH1SS1 Katalog tesla diod MH7442 MH7404 MA0403 MAA723 MH74S74
Contextual Info: POLOVODICOVÉ S O U C Á S T K Y PftEDPIS PRO P Ä JEN l Polovodicove soucdstky Jsou velml choulostlvd na nadmernS otepleni. Proto, aby nedochazelo k je jich poskozeni, do p o ruiuje se zachovat tento postup pfl pd jenf: Konce pnvodii je nutno predem ocinovat v delce 4 - 5

LT3973-3.3

Abstract: L1117T-3.3 LI-CAM-IMX136-1.8 SFH7781-1/2/3 LM3670MFX-0.8 LT3971-3.3 LT1432-3.3
Contextual Info: m o le x £ros$ p eference Numbers Old P a r t i Hew Part i O U P a rti New Part i Old Part # New Part i Old P a r t i 07262M 07 84581-0001 0 93 5 6 K 0 7 8 45 6 6 -5 03 5 0 94 6 2 K 0 7 84566-5041 09566M 07 8 4 5 6 6 -0 0 6 5 07264M 07 8 4 5 8 1 -0 00 0 0 93 5 7 K 0 7

Power INVERTER schematic

Abstract: hcpl7100 HCPL-7100
Contextual Info: W h n t HEW LETT wL 'k M P A C K A R D High Speed CMOS Optocouplers Technical Data HCPL-7100 HCPL-7101 Features Description • 1 |im CMOS IC Technology • Compatibility w ith All +5 V CMOS and TTL Logic Families • No External Components Required for Logic Interface