JTAG ICE Search Results

jtag mhz

Abstract: MOUNTAIN-ICE ISA slot
Contextual Info: Mountain-ICE TM ISA-Based Emulator for SHARC DSP Processors! The Mountain-ICETM is the industry’s first scan-based, JTAG emulator designed specifically to support emulation across multiple SHARC® DSP processors. An enhanced 3V/5V JTAG pod and cable provide a non-intrusive interface to any

sparclite

Abstract: MB86930 CB123 XCB100 tl 741 X0010 ASR17 EWS300-24 instruction manual
Contextual Info: SECTION 1 MB86930 Chapter 7: Instruction Set Chapter 8: JTAG MB86930 - SPARClite User’s Manual SPARClite User’s Manual Chapter 7: Instruction Set 7.1 Suggested Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

ARM9TDMI

Abstract: ARM920T rom ARM920T ARM920TTM atmel jtag ice usb ARM920T instruction DSP GROUP
Contextual Info: S YSTEM L EVEL I NTEGRATION ARM920TTM MICROCONTROLLER ARM920T Instruction Memory Manageme nt Unit Instruction Cache Embedded ICE Instruction Bus AMB Bus In A terface JTAG Data Bus ARM9TDMI Core Up to 200 MIPS at 180 MHz on 0.18-micron 1.8V CMOS technology

C8051F236DK

Abstract: 8051-COMPATIBLE C8051F236
Contextual Info: C8051F236 Mixed-Signal 8KB ISP FLASH MCU PRELIMINARY ANALOG PERIPHERALS Two Comparators - Programmable Hysteresis - Configurable to Generate Interrupts or Reset VDD Monitor and Brown-out Detector ON-CHIP JTAG EMULATION - On-Chip Emulation Circuitry Facilitates Full Speed,

DSP JTAG

Abstract: summit-ICE Equivalent adi
Contextual Info: Summit-ICE TM PCI-Based Emulator for Analog Devices JTAG DSPs KEY FEATURES OVERVIEW this product is the natural choice n PCI emulator card The Summit-ICE system is the for ADI DSP development. n Rugged high-speed 3V/5V scan-based flexible emulator cable and pod 5 feet

Contextual Info: fax id: 6148 CYPRESS PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — ts = 4.5 ns — tco = 5.0 ns • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ Product-term clocking IEEE1149.1 JTAG boundary scan

Contextual Info: Revision 5 Fusion Family of Mixed Signal FPGAs Features and Benefits In-System Programming ISP and Security • ISP with 128-Bit AES via JTAG • FlashLock Designed to Protect FPGA Contents High-Performance Reprogrammable Flash Technology • • • •

SN54ABT8652

Abstract: SN74ABT8652
Contextual Info: SN54ABT8652, SN74ABT8652 « SCAN TEST d e v ic e s WITH OCTAL BUS TRANSCEIVERS AND REGISTERS - _ • Members of the Texas Instruments SCOPE Family of Testability Products • Compatible With the IEEE Standard 1149.1-1990 JTAG Test Access Port and

INTELDX4 write-through

Abstract: 242202
Contextual Info: in t e i EMBEDDED WRITE-BACK ENHANCED lntelDX4 PROCESSOR Up to 100 MHz Operation Data Bus Parity Generation and Checking Integrated Floating-Point Unit Speed-Multiplying Technology Boundary Scan JTAG 32-Bit RISC Technology Core 3.3-Volt Processor, 75 MHz, 25 MHz

Contextual Info: M B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR APRIL, 1996 • On-chip clock generator circuit FEATURES • JTAG test interface • 25 and 50 MHz versions • Emulator support hardware • Clock doubler for 50 MHz version • Single vector trapping

Contextual Info: SN74ABT18646 SCAN TEST DEVICE WITH 18-BIT TRANSCEIVER AND REGISTER SCBS131A – AUGUST 1992 – REVISED JANUARY 2002 D D D D Member of the Texas Instruments Widebus Family Compatible With IEEE Std 1149.1-1990 JTAG Test Access Port and Boundary-Scan Architecture

pal 014

Contextual Info: PRELIMINARY COM’L: -15/20 MACH355-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 144 Pins In PQFP ■ Up to 20 product terms per function, with XOR ■ JTAG, 5-V, In-circuit programmable ■ Flexible clocking

Contextual Info: W CYPRESS CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Functional Description Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

transistor P7o

Abstract: H30P 54SX16
Contextual Info: Preliminary v 1 .0 54SX Family FPGAs Features • Unique, In-System Diagnostic and Debug Facility with Silicon Explorer High Perform ance • JTAG Boundary Scan Testing In Compliance with IEEE • 320 MHz I nternal Performance • 4.0 ns Cl ock-to-Out Pin-to-Pin

summit-ICE

Abstract: DSP JTAG ADSP-21065L White Mountain DSP Analog Solutions ADSP21160
Contextual Info: Summit-ICE TM PCI-Based Emulator for SHARC DSP Processors! The Summit-ICETM system is the industry’s first Local Bus PCI card emulator designed to support emulation across Analog Devices ADI SHARC® DSP processors. A shielded 3V/5V JTAG pod and cable provides a nonintrusive interface to any ADSP-2106x SHARC DSP or

Contextual Info: Xgjf PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD — tPD = 15 ns Features — ts = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 8 ns Product-term clocking IEEE 1149.1 JTAG boundary scan

Contextual Info: PRELIMINARY Ultra37256 3F C Y P R E S S UltraLogic 256-Macrocell ISR™ CPLD Features • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ — JTAG compliant on board programming — Design changes don’t cause pinout changes

PSDSoft

Abstract: UPSD3454EVB40T6 BC POWER MODULE uPSD3454E-40U6 UPSD3433EVB40U6 L51_BANK.A51 TQFP52 TQFP80 uPSD3422E-40T6 uPSD3422E-40U6
Contextual Info: uPSD34xx Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic Features summary • Fast 8-bit Turbo 8032 MCU, 40 MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40MHz 5V – JTAG Debug and In-System Programming

CY37384

Abstract: CY37384V L0651
Contextual Info: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.

A54 ZENER

Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Contextual Info: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents

TQFP52

Abstract: TQFP80 uPSD3422E-40T6 uPSD3422E-40U6 uPSD3422EV-40T6 uPSD3422EV-40U6 uPSD3433E-40T6 uPSD34xx Turbo-8032
Contextual Info: uPSD34xx Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic DATA BRIEFING FEATURES SUMMARY • ■ ■ FAST 8-BIT TURBO 8032 MCU, 40MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40MHz 5V – JTAG Debug and In-System

JTAG

Abstract: CY37032
Contextual Info: UltraLogic 32-Macrocell ISR™ CPLD — ts = 3 ns Features — tco = 4 ns • 32 macrocells in two logic blocks • In-System Reprogrammable™ ISR™ • Product-term clocking • IEEE 1149.1 JTAG boundary scan • Programmable slew rate control on individual l/Os

bj 94 131- 6

Abstract: DO96
Contextual Info: . „ n « PRELIMINARY Ultra37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: . _ n « PRELIMINARY Ultra37032 UltraLogic 32-Macrocell ISR™ CPLD — ts = 3 ns Features — tco = 4 n s • 32 macrocells in two logic blocks • In-System Reprogrammable™ ISR™ • • • • • • • — JTAG-compliant on-board programming