JLCC 32 R Search Results

Contextual Info: HANBit HMF51232J4 FLASH-ROM MODULE 2MByte 512K x 32-Bit – 68-Pin JLCC Part No. HMF51232J4 GENERAL DESCRIPTION The HMF51232J4 is a high-speed flash read only memory (FROM) module containing 524,288 words organized in a x32bit configuration. The module consists of four 512Kx 8 FROM mounted on a 68 -pin, JLCC FR4-printed circuit board.

Contextual Info: SRAM FT5C4008 L 512K x 8 High Speed SRAM PIN ASSIGNMENT (Top View) SRAM MEMORY ARRAY . SPECIFICATION 32-Pin DIP , 32-Pin LCC JLCC 32-Pin CSOJ • • Comm,Ind, Mil • MIL STD-883 M5004 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss FEATURES •

5962-8606302XX

Abstract: AT27C256R-20DC 5962-86063 AT27C256R70DC AT27C256R-20PI AT27C256R20PI AT27C256R25LI 5962-8606305XX AT27C256R-20/XA
Contextual Info: AT27C256R Features • • Fast Read Access Time - 70 ns Low Power CMOS Operation 100 nA max. Standby 20 mA max. Active at 5 MHz • wide Selection of JEDEC Standard Packages Including: 28-Lead 600-mil Cerdip, OTP Plastic DIP, SOIC, or TSOP 32-Pad LCC, 32-Lead JLCC and OTP PLCC

Contextual Info: Features • Bipolar Speed in JEDEC Standard EPROM Pinout Read Access Time • 55ns 28-Lead 600 mil CERDIP and OTP Plastic DIP 32-Pad LCC, JLCC and OTP PLCC • Low Power CMOS Operation 100 jiA max. Standby 50 mA max. Active at 10 MHz • High Output Drive Capability

AT27C512R-15DC

Abstract: AT-27C512R-12LM
Contextual Info: AT27C512R Features • Fast Head Access Time - 90 ns • Low Power CMOS Operation 100 jiA max. Standby 20 mA max. Active at 5 MHz • Wide Selection of JEDEC Standard Packages 28-Lead 600-mil Cerdlp and OTP Plastic DIP, SOIC, or TSOP 32-Pad LCC, 32-Lead JLCC and OTP PLCC

Contextual Info: 128K x 32 EEPROM Module PUMA 2/67E4001/A/B -12/15/20 Issue 4.3 : January 2001 Description Available in PGA Puma 2 , and JLCC (Puma 67) footprints, the Puma *E4001 is a 4 Mbit EEPROM module user configurable as 128K x 32, 256K x 16 or 512K x 8. Available with access times of 120, 150

Contextual Info: 128K x 32 EEPROM Module PUMA 2E4001 -12/15/20 PUMA 67E4001/A/B -12/15/20 PUMA 77E4001/A/B -12/15/20 Elm Road, West Chirton, North Shields, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Description Available in PGA (Puma 2), JLCC (Puma 67) and

Contextual Info: Features • Fast Read Access Time - 70ns • Low-Power CMOS Operation • • • • • • • – 100 µA max. Standby – 20 mA max. Active at 5 MHz JEDEC Standard Packages – 28-Lead 600-mil Windowed CDIL – 32-Lead Windowed LCC/JLCC – 28-Lead Custom

77E4001

Abstract: pumas E4001
Contextual Info: 128K x 32 EEPROM Module PUMA 2E4001 -12/15/20 PUMA 67E4001/A/B -12/15/20 PUMA 77E4001/A/B -12/15/20 Elm Road, West Chirton, North Shields, Tyne & Wear NE29 8SE, England Tel. +44 0191 2930500 Fax. +44 (0191) 2590997 Description Available in PGA (Puma 2), JLCC (Puma 67) and

Contextual Info: Features • Fast Read Access Time - 45 ns • Low-Power CMOS Operation – 100 µA max. Standby – 25 mA max. Active at 5 MHz FT27C010L – 35 mA max. Active at 5 MHz (FT27C010) • JEDEC Standard Packages – 32-Lead CDIL/LCC/JLCC +Custom Ceramic packages

Memory

Abstract: FT27C010 L20062
Contextual Info: Features • Fast Read Access Time - 45 ns • Low-Power CMOS Operation – 100 µA max. Standby – 25 mA max. Active at 5 MHz FT27C010L – 35 mA max. Active at 5 MHz (FT27C010) • JEDEC Standard Packages – 32-Lead CDIL/LCC/JLCC +Custom Ceramic packages

Contextual Info: 128K x 32 SRAM Module TIGA2S4000 -20/25/35 TIGA6S4000/A/B-20/25/35 TIGA7S4000/A/B-20/25/35 Force Technologies Ltd. www.forcetechnologies.co.uk Tel. +44 0 1264 731200 Fax. +44 (0)1264 731444 Issue 1 2005 Description Features Available in PGA (TIGA 2), JLCC (TIGA 6) and

sram 1mbyte 3.3v

Abstract: HMS25632J2V 256KX
Contextual Info: HANBit HMS25632J2V SRAM MODULE 1Mbyte 256K x 32-Bit 3.3V, 68-Pin JLCC Packaging Part No. HMS25632J2V GENERAL DESCRIPTION The HMS25632J2V is a high-speed static random access memory (SRAM) module containing 262,144 words organized in a x32-bit configuration. The module consists of two 256K x 16 SRAMs mounted on a 68-pin, double-sided, FR4-printed circuit

2S4000

Contextual Info: 128K x 32 SRAM Module PUMA 2/67S4000/A-020/025/35 Issue 4.4 : April 2001 Description Features Available in PGA PUMA 2 and JLCC (PUMA 67) footprints the PUMA *S4000 is a 4 Mbit SRAM module, user configurable as 128K x 32, 256K x 16 or 512K x 8. The device is available with fast access

Contextual Info: 128K x 32 EEPROM Module TIGA 2E4001 -12/15/20 TIGA 6E4001/A/B -12/15/20 TIGA 7E4001/A/B -12/15/20 Description Available in PGA TIGA 2 , JLCC (TIGA 1/6) and Gullwing (TIGA 7) footprints, the TIGA *E4001 is a 4 Mbit EEPROM module user configurable as 128K x 32, 256K x 16 or 512K x 8. Available with

PUMA77S4000

Abstract: 2S4000
Contextual Info: 128K x 32 SRAM Module PUMA 2/67/77S4000/A-020/025/35 11403 West Bernado Court, Suite 100, San Diego, CA 92127. Tel No: 001 858 674 2233, Fax No: (001) 858 674 2230 Description Issue 4.3 : December 1999 Features Available in PGA (PUMA 2), JLCC (PUMA 67) and •

HMS51232J4

Contextual Info: HANBit HMS51232J4 SRAM MODULE 2Mbyte 512K x 32-Bit , 68-Pin JLCC Packaging Part No. HMS51232J4 GENERAL DESCRIPTION The HMS51232J4 is a static random access memory (SRAM) module containing 524,288 words organized in a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 68-pin, single-sided, FR4-printed circuit board.

HMS25632J2

Contextual Info: HANBit HMS25632J2 SRAM MODULE 1Mbyte 256K x 32-Bit , 5V, 68-Pin JLCC Design Part No. HMS25632J2 GENERAL DESCRIPTION The HMS25632J2 is a high-speed static random access memory (SRAM) module containing 262,144 words organized in a x32-bit configuration. The module consists of two 256K x 16 SRAMs mounted on a 68-pin, double-sided, FR4-printed circuit

HMS51232J4A

Contextual Info: HANBit HMS51232J4A SRAM MODULE 2Mbyte 512K x 32-Bit , 68-Pin JLCC Packaging Part No. HMS51232J4A GENERAL DESCRIPTION The HMS51232J4A is a static random access memory (SRAM) module containing 524,288 words organized in a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 68-pin, single-sided, FR4-printed circuit board.

pin diagram ic 7420

Abstract: 7420 ic
Contextual Info: PUMA 67F16006-90/12/15 /2 s mosaic 512Kx 32 FLASH MODULE Issue 4.0 September 1995 semiconductor, inc. Description The PUMA 67F16006 is a 16 Megabit CMOS 5.0V only FLASH Module in a 6 8 pin JLCC package, with access times of 90,120 and 150 ns. The oyput width is configurable as 8 ,1 6 ,3 2 bit wide using

SRAM 6T

Abstract: MSM8128 "32K x 8" SRAM dil SRAM 35ns "32K x 8" SRAM PLCC 2035 puma 5 128k x 8 eeprom JLCC
Contextual Info: Part Numbering M S M 8512 SC X L MB - 10 1. 2. 3. 4. 1. 2. Speed 7. 6. 5. TECHNOLOGY 5. PINOUT ARRANGEMENT The memory technology is represented by a single character:- This field identifies the mechanical arrangement of the device pinout:- S D E U blank E

EP1210D

Abstract: EP320D ep1800g EP320P EP1800L EPS448D EP6000 EP900D
Contextual Info: EP ID PACKA6E PIHS MACRO CELLS IREGISTERS BURIED REGISTERS INPUTS I/O M Hz Imix Icc mA STANOBY Icc mA EP1800J EP1800L EP1800G JLCC PLCC PGA 68 68 68 48 48 48 16 16 16 16 16 16 48 48 48 25.0 25.0 25.0 30.0 30.0 30.0 0.15 0.15 0.15 EP1210D EP1210P EP1210J EP1210L

jlcc 32 R

Abstract: CERAMIC CHIP CARRIER LCC 28
Contextual Info: 1 Megx 1 CMOS SRAM molaic MSM11000-020/025 Issue 1.0 : February 1993 ADVANCE PRODUCT INFORMATION S e m ic o n d u c to r Inc. 1,048,576 x 1 CMOS High Speed Static RAM Pin Definition Package Type: 'K'.V A0 1 A1 2 A21 A3 « A4 5 AS 6 NC 7 »8 1 A7 S AS 10 A9 11

68-JLCC package

Contextual Info: 11 Data Sheet General Information Æftl ^ n^\ Thermal Resistance °C/W September 1991, ver. 2 In tr o d u c tio n T a b l e s 1 a n d 2 g i v e t h e r m a l re s is t a n c e d a ta for A lt e r a C l a s s i c a n d M A X 5 0 0 0 E P L D s . All th e rm a l c h a ra c te r is tics are m e a s u r e d u s in g the T e m p e r a t u r e