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    x32-bit Datasheets

    Top Results (6)

    Part ECAD Model Manufacturer Description Download Buy
    SN74AXC2T45DCTR Texas Instruments Dual-bit dual-supply bus transceiver with configurable voltage translation Visit Texas Instruments Buy
    SN74AXC2T45DCUR Texas Instruments Dual-bit dual-supply bus transceiver with configurable voltage translation Visit Texas Instruments Buy
    SN74AXC1T45DCKR Texas Instruments Single-bit dual-supply bus transceiver 6-SC70 -40 to 125 Visit Texas Instruments Buy
    SN74AXC1T45DBVR Texas Instruments Single-bit dual-supply bus transceiver 6-SOT-23 -40 to 125 Visit Texas Instruments Buy
    SN74AXC1T45DTQR Texas Instruments Single-bit dual-supply bus transceiver 6-X2SON -40 to 125 Visit Texas Instruments Buy
    SN74LVC2T45QDCURQ1 Texas Instruments Automotive Catalog Dual-Bit Dual Supply Transceiver with Configurable Voltage Translation 8-VSSOP -40 to 125 Visit Texas Instruments Buy

    x32-bit Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    2004 - DDR2 x32

    Abstract: ELPIDA DDR2 Datasheet Unbuffered DDR2 SDRAM DIMM DDR2 layout 84 FBGA outline DDR2 SDRAM "DDR2 SDRAM" 84 FBGA DDR2 DDR2 x16
    Text: TSOP(II)/FBGA Support x32-bit I/O 512Mb DDR2 SDRAM Elpida Memory has delivered the 512Mb DDR2 SDRAM with x32-bit I/O configuration samples. In the past a DDR2 controller with x32-bit wide interface required two x16-bit I/O DRAMs. Now, Elpida offers a 512Mb DDR2 SDRAM with x32-bit I/O configuration as a one-chip solution. The advantages of this x32-bit solution over a two 256-megabit DDR2 (with x16-bit , better signal quality Elpida's new x32-bit DDR2 product realizes a simpler board layout and it can


    Original     		PDF 200/266/333/400/533MHz 400/533/667/800/1066Mbps x4/x8/x16/x32 100/133/166/200/250MHz 200/266/333/400/500Mbps E0474ED0 512Mb DDR2 x32 ELPIDA DDR2 Datasheet Unbuffered DDR2 SDRAM DIMM DDR2 layout 84 FBGA outline DDR2 SDRAM "DDR2 SDRAM" 84 FBGA DDR2 DDR2 x16

    2005 - DDR2 x32

    Abstract: ELPIDA DDR3 DDR3 DRAM layout ddr3 sdram chip datasheets 128mb 512MB xdr elpida DRAM elpida ELPIDA DDR2
    Text: and with low power consumption, x32-bit I/O SDRAM is ideal for the strict space requirements of , processing can be optimized by using x16-bit or x32-bit I/O SDRAM, or DDR SDRAM. We also provide "Bare Chip , 512Mb 1Gb 2Gb As of August, 2008 Low Power Consumption & Slim Layout ( x32-bit I/O 512Mb DDR2 SDRAM) Elpida developed x32-bit I/O 512Mb DDR2 SDRAM to meet the need for small-size consumer electronics that feature 1.8V low-voltage operations and low-power consumption. Because the new x32-bit


    Original     		PDF x32-bit 256Mb x16-bit 229mA 258mA 172mA 256Mb 512Mb E0652E90 DDR2 x32 ELPIDA DDR3 DDR3 DRAM layout ddr3 sdram chip datasheets 128mb 512MB xdr elpida DRAM elpida ELPIDA DDR2

    2005 - sdram pin voltage

    Abstract: DRAM elpida elpida SDRAM
    Text: low power consumption, x32-bit I/O SDRAM is ideal for the strict space requirements of today , x32-bit I/O SDRAM, or DDR SDRAM. We also provide "Bare Chip" products for use in SiP design


    Original     		PDF 210mA 140mA 256Mb 512Mb E0652E40 sdram pin voltage DRAM elpida elpida SDRAM

    TM2I

    Abstract: TM90A mn1a7t0200 TM10 TM11 FLGA152-C-1111 A7133 AN-231
    Text: □ MN1A7T0200 ■Type MN1A7T0200 1 ROM (x8-Bit / x16-Bit / x32-Bit ) Max 16 M in total 1 RAM (x8-Bit / x16-Bit / x32-Bit ) External ROM and RAM 1 Minimum Instruction Execution Time 100 ns (at 2.3 V to 2.7 V, 20 MHz) I Timer Counter • RESET • IRQO to 5 • NMI • Timer 0 to 9 Underflow • Timer 8 to 9 Compare Capture A • Timer 8 to 9 Compare Capture B • Serial ch 0 to 2 Transmission • Serial ch 0 to 2 Reception > Serial ch 0 to 2 in Communication State • Serial ch 0 to 2 Modem Status â


    OCR Scan     		PDF MN1A7T0200 x16-Bit x32-Bit) 16-Bit TM80B TM80A TM90B TM2I TM90A mn1a7t0200 TM10 TM11 FLGA152-C-1111 A7133 AN-231

    dq35j

    Abstract: Nippon capacitors
    Text: No file text available


    OCR Scan     		PDF MM2M0J32L MM2M0J36L 32bit 36bit MM1M0J32L/J36L MM2M0J32UMM2M0J36L x32biVx36blt dq35j Nippon capacitors

    MN19412A

    Abstract: MN19411 PGA144-C-S15U L78 H mn19412 mn19413 MN1900
    Text: Microcomputers Digital Signal Processors (D S P ), M N 1900/1920/1930 Family ROM (K X32-bit ) RAM1 ( X 16-bit) RAM2 ( X 1 6-bit) Category Type No. Speed (ns) Supply Voltage (typ) Package No. Evaluator Remarks (V) 512 built-in, 4K ext. 512 built-in, 4K ext M N19091 A M N19041 A 8 e x t. 258 built-in 258 built-in 514 built-in 514 built-in 258 built-in 1026 built-in 450 built-in 514 built-in 100 4.75 to 5.25 PGA144-C-S15U 4.75 to 5.25 QFP084-P-1818 LI 03 L72


    OCR Scan     		PDF X32-bit) 16-bit) N19091 N19041 PGA144-C-S15U QFP084-P-1818 MN19091A PGA144-C-S15U N19091ARAM N19041ARAM MN19412A MN19411 L78 H mn19412 mn19413 MN1900

    AL460A

    Abstract: AL460A-7 25X2 AL460A-13-EVB-A0 al460 LP3852 MALE PIN HEADER 25X2
    Text: double buffer mode (4M x32-bit upper and lower frames access) Maximum 4.8 Gbps throughput


    Original     		PDF AL460A AL460A-7 32-bits. 50-pin 32-bit x32-bit 25X2 AL460A-13-EVB-A0 al460 LP3852 MALE PIN HEADER 25X2

    SSOP-90

    Abstract: MBM29PL3200BE MBM29PL3200TE fbga84
    Text: 1(: 352'8&76 0%03/7(%( · · · 32 M-Bit Page Mode Flash Memory with x16/ x32-Bit Bus Width: MBM29PL3200TE/BE · · · · · · · · · · · · · · · , existing x32 mask ROM products · · · · · · · · · x16-bit or x32-bit bus widths , earlier x8-/x16-bit to x16-/ x32-bit , providing the ability to process large volumes of · · · · · , 0%03/7(%( · · · · · · x16- or x32-Bit Bus Width · · · The DW/ W pin is


    Original     		PDF x16/x32-Bit MBM29PL3200TE/BE 32-bit SSOP-90, FBGA-84 ns/35 MBM29PL3200BE ns/90 MBM29PL3200TE SSOP-90 MBM29PL3200BE MBM29PL3200TE fbga84

    HMS51232J4V

    Abstract: marking HX 6 pin KXY 23
    Text: HANBit HMS51232J4V HAN SRAM MODULE 2Mbyte (512Kx32Bit), 68-Pin JLCC Packaging,3.3V BIT Part No. HMS51232J4V GENERAL DESCRIPTION The HMS51232J4V is a static random access memory (SRAM) module containing 524,288 words organized in a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 68-pin, single-sided, FR4printed circuit board. Four chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module's 4 bytes independently. Output enable (/OE) and


    Original     		PDF HMS51232J4V 512Kx32Bit) 68-Pin HMS51232J4V x32-bit 68-pin, x32bit 32bit marking HX 6 pin KXY 23

    Nippon capacitors

    Abstract: No abstract text available
    Text: No file text available


    OCR Scan     		PDF MM1M0J32L/MM1M0J36L 32bit 36bit MM1M0J32L/J36L MM1M0J13- 57REF MM1M0J32UMM1M0J36L x32blt/x36bit CIQCI02D2 Nippon capacitors

    Not Available

    Abstract: No abstract text available
    Text: HANBit HMF51232J4V FLASH-ROM MODULE 2MByte (512K x32-Bit ) ­ 68-Pin JLCC Part No. HMF51232J4V GENERAL DESCRIPTION The HMF51232J4V is a high-speed flash read only memory (FROM) module containing 524,288 words organized in a x32bit configuration. The module consists of four 512Kx 8 FROM mounted on a 68-pin, JLCC FR4-printed circuit board. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine, which controls the


    Original     		PDF HMF51232J4V x32-Bit) 68-Pin HMF51232J4V x32bit 512Kx 68-pin,

    4mx16

    Abstract: HYM7V65401 8Mx72 PC100 16Mx64 1MX16BIT MX321 7V651601 Y57V641620HG y57v641620
    Text: , 3.3V, ET_Part 4Mx16-bit, 4K Ref., 4Banks, 3.3V 2Mx32-bit, 4K Ref., 4Banks, 3.3V 2M x32-bit , 4K Ref


    OCR Scan     		PDF HY57V 161610DTC HY57V161610DTC-I 1Mx16-bit, x16-bit, HYM41V33100BTWG HYM41V33100DTYG PC133 1Mx32, 1Mx16 4mx16 HYM7V65401 8Mx72 PC100 16Mx64 1MX16BIT MX321 7V651601 Y57V641620HG y57v641620

    HMS51232M4L

    Abstract: 72-pin simm
    Text: HANBit HMS51232M4L HAN SRAM MODULE 2Mbyte (512K x 32-Bit), BIT SIMM 5V LOW POWER, 72-Pin Part No. HMS51232M4L GENERAL DESCRIPTION The HMS51232M4L is a static random access memory (SRAM) module containing 524,288 words organized in a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 72-pin, single-sided, FR4printed circuit board. The HMS51232M4L also support low data retention voltage for battery back-up operations with low data retention current


    Original     		PDF HMS51232M4L 32-Bit) 72-Pin HMS51232M4L x32-bit 72-pin, 32bit 72-pin simm

    HMS51232M4V

    Abstract: HMS51232Z4V
    Text: HANBit HMS51232M4V/Z4V HAN SRAM MODULE 2Mbyte (512K x 32-Bit), 3.3V BIT Part No. HMS51232M4V, HMS51232Z4V GENERAL DESCRIPTION The HMS51232M4V/Z4V is a high-speed static random access memory (SRAM) module containing 524,288 words organized in a x32-bit configuration. The module consists of four 512K x 8 SRAMs mounted on a 72-pin, single-sided, FR4-printed circuit board. PD0 to PD3 identify the module's density allowing interchangeable use of alternate density, industry- standard


    Original     		PDF HMS51232M4V/Z4V 32-Bit) HMS51232M4V, HMS51232Z4V HMS51232M4V/Z4V x32-bit 72-pin, 32bit HMS51232M4V HMS51232Z4V

    2004 - Elpida LPDDR2 Memory

    Abstract: lpddr2 datasheet elpida lpddr2 lpddr2 ELPIDA mobile dram LPDDR2 ddr2 ram Jedec lpddr2 lpddr2 mcp ELPIDA mobile DDR LPDDR2 1Gb Memory
    Text: high-speed operation max. x16-bit / x32-bit configurations are available Refresh current ATSCR


    Original     		PDF E0566E80 Elpida LPDDR2 Memory lpddr2 datasheet elpida lpddr2 lpddr2 ELPIDA mobile dram LPDDR2 ddr2 ram Jedec lpddr2 lpddr2 mcp ELPIDA mobile DDR LPDDR2 1Gb Memory

    2004 - ELPIDA mobile DDR

    Abstract: elpida MCP market Elpida Memory E0566E50 circuit mobile phone Elpida mobile DRAM elpida
    Text: RAM. 1.8V operation PASR ATSCR x16-bit / x32-bit configurations are available New functions


    Original     		PDF 512Mb, E0566E50 ELPIDA mobile DDR elpida MCP market Elpida Memory E0566E50 circuit mobile phone Elpida mobile DRAM elpida

    mt808

    Abstract: 88c marking
    Text: The M T8D88C132H(S) and M T16D88C232H(S) comprise a family of DRAM cards organized in x32-bit m emory , ) comprise a fam ily of DRAM cards organized in x32-bit m emory arrays (RASO = RAS2). They also m aybe , bank control procedures are implem ented by interleaving both RAS lines. M ost x32-bit applications use


    OCR Scan     		PDF 88-pin MT8D68C132H MT16D88C232H mt808 88c marking

    TM610

    Abstract: MN103004J sbti TM210 MN1030F04K
    Text: □ MN103004J / 04K / F04K 1 Type MN103004J / 04K / F04K 1 Command ROM (x64-Bit) 192 KB/128 KB/256 KB (Flash) 1 Data RAM ( x32-Bit ) 4 KB/10 KB/12 KB 1 Minimum Instruction Execution Time MN103004J/04K: MN103004J/04K: MN1030F04K: 30 ns (at 2.2 V, 33 MHz) 25 ns (at 3.0 V, 40 MHz) 36 ns (at 3.0 V, 28 MHz, 40 MHz (under development) 1 Interrupts •RESET • IRQx8 • N • System error Ml x 1 • Timerx22« Input Capture x 14 •PWMx4»SIFx 16« DMACx4 • WDT • A/D Timer Counter 0 to 3: 32-Bit x 1


    OCR Scan     		PDF MN103004J x64-Bit) KB/128 KB/256 x32-Bit) KB/10 KB/12 MN103004J/04K: TM610 sbti TM210 MN1030F04K

    Not Available

    Abstract: No abstract text available
    Text: □ M N 1 0 3 0 0 0 MN103000 1 Type 1 Command RAM (x64-bit) 16K 1 Data RAM ( x32-bit ) 16K 1 Minimum Instruction Execution Time 16.7ns (at 3.3V, 60MHz) 1 Interrupts •RESET • IRQ x8 • NMI • Timer x28 * SIF x4 - DIVIAC x4 • WDT »A/D »System error I Timer Counter Tim er Counter 0 to 3: 32-bit x 1 (Interval Timer, Event Count, Timer Output, Interrupt, Clock Source for Serial l/F, A/D Conversion Trigger) Clock Source.I0CLK, External Clock Input


    OCR Scan     		PDF MN103000 x64-bit) x32-bit) 60MHz) 32-bit QFP160-P-2828B P93/IR03/ADTRG P94/DK P87/SY1OT2/TM8IOA

    M-8G

    Abstract: HMS1M32M8G HMS1M32Z8
    Text: HANBit HMS1M32M8G/Z8 HAN SRAM MODULE 4Mbyte(1M x 32-Bit) BIT Part No. HMS1M32M8G, HMS1M32Z8 GENERAL DESCRIPTION The HMS1M32M8G/Z8 is a high-speed static random access memory (SRAM) module containing 1,048,576 words organized in a x32-bit configuration. The module consists of eight 1M x 4 SRAMs mounted on a 72-pin, double-sided, FR4-printed circuit board. PD0 to PD3 identify the module's density allowing interchangeable use of alternate density, industry- standard modules. Eight


    Original     		PDF HMS1M32M8G/Z8 32-Bit) HMS1M32M8G, HMS1M32Z8 HMS1M32M8G/Z8 x32-bit 72-pin, 32bit M-8G HMS1M32M8G HMS1M32Z8

    2000 - ST 9336

    Abstract: Automatic car ADSP-21161 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21065 ADSP-21160M ADSP-21161N ADSP-21161 assembler
    Text: Packing logic supports data access and instruction fetch from x8-, x16-, and x32-bit width external


    Original     		PDF ADSP-21161 32-Bit 32-bit ADSP-21x6x 40-bit ADSP-21062 ST 9336 Automatic car ADSP-21161 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21065 ADSP-21160M ADSP-21161N ADSP-21161 assembler

    832HS

    Abstract: No abstract text available
    Text: organized in x32-bit m em ory arrays. These DRAM cards are 2-inch-long bu fferless v ersions of the JE D E C , ) and M T 16D 88C 232H / 832H(S) comprise a family of DRAM cards organized in x32-bit m em ory arrays , RAS lines. M ost x32-bit applications use the sam e signal to control the CA S inputs. RASO and RAS1


    OCR Scan     		PDF MT8D88C132H/432H MT16D88C232H/832H 88-pin 832HS

    vrc5476

    Abstract: VR12000 VR7701 VRC5074 VR4181 NEC VR10000 "embedded dram" nec MIPS64 VR4121 vrc4375
    Text: SEC/DED ECC · 100 MHz or 133 MHz SDR/DDR memory · Maximum 1 Gb x 8-, x16-, x32-bit width DRAM ·


    Original     		PDF VR7701 64-Bit VR7701TM PD30771) 64-Bit vrc5476 VR12000 VR7701 VRC5074 VR4181 NEC VR10000 "embedded dram" nec MIPS64 VR4121 vrc4375

    QFP160-P-2828B

    Abstract: MN103000
    Text: □ MN103000 1 Type MN103000 ■Command RAM (x64-bit) 16K ■Data RAM ( x32-bit ) 16K 1 Minimum Instruction Execution Time 16.7ns (at 3.3V, 60MHz) ■Interrupts •RESET • IRQ x8 • NMI • Timer x28 »SIFx4 • DMAC x4 • WDT • A/D »System error Timer Counter 0 to 3: 32-bit x 1 (Interval Timer, Event Count, Timer Output, Interrupt, Clock Source for Serial l/F, A/D Conversion Trigger) Clock Source.IOCLK, External Clock Input, Underflow of Timer Counter Interrupt Source.Underflow of Timer


    OCR Scan     		PDF MN103000 x64-bit) x32-bit) 60MHz) 32-bit P93/IRQ3/ADTRG P94/DK QFP160-P-2828B MN103000

    Not Available

    Abstract: No abstract text available
    Text: □ MN103001G / MN1030F01K MN103001G / MN1030F01K 1 Type 1 Command RAM (x64-bit) 128K/256K (Flash) 1 Data RAM ( x32-bit ) 8K 1 Minimum Instruction Execution Time 16.7ns (at 3.3V, 60MHz) 1 Interrupts •RESET * IRQ x8 • NMI *T im erx1 8 * SIF x8 -WDT *A/D »System error I Timer Counter Tim er Counter 0 to 3: 32-bit x 1 (Interval Timer, Event Count, Timer Output, Interrupt, Clock Source for Serial l/F, A/D Conversion Trigger) Clock Source.I0CLK, IOCLK/8


    OCR Scan     		PDF MN103001G MN1030F01K MN103001G x64-bit) 128K/256K x32-bit) 60MHz) 32-bit IOCLK/32,
    ...

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