JJJJ Search Results

VP0545N2

Abstract: VP0545N3
Contextual Info: _ J jjjj ^ _ VP0545 VP0550 _ P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package b v dss/ ^D S O N b v dgs (max) (min) TO-39 TO-92 DICE+ -450V 125Q -100mA VP0545N2 VP0545N3 VP0545ND -500V 125Q -100mA VP0550N2 VP0550N3

Contextual Info: SPECIFICATION D B D e to il. 33267 17/11/05 31058 8 -J U L -0 2 Hod. Dot. JMDR CV Nome Dal. Nome 8 -J U L -0 2 CV Insp. A ll Dim. in m Stand. Orig. Size DIN A 4 HARTING EURL F-95972 Par i s JjJJJj D- Sub, mal e, s t r a i g h t 15 Pol es, sol der buckets,

CN078S-081-0022

Abstract: CN078S cn078 CN078A-1001 CN078P-061-0001 lan transistor 0800001 CN078S-080-0110 RJ45 LAN RJ45-IP67
Contextual Info: CN078 LAN °C CN078 RJ45 RJ45 IP67 IP67 LAN CAT5/100Mbps FA 2 LAN CN078 JJJJJJJJJJJJJJJJJ| |JJJJJJJJJJJJJJJJJ CN078A-2003 | CN078A-2010 | CN078A-2023 |

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM N K t t ♦ < ij / 5; PRELIMINARY *^ ' CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

IXGH17N100

Contextual Info: BIXYS jjjjjB jjj Low VCHH0IGBT High speed IGBT IXGH/IXGM17N100 IXGH/IXGM17 N100A VC E S ^C25 v C E sat 1000 V 1000 V 34 A 34 A 3.5 V 4.0 V « Symbol Test Conditions Maximum Ratings VCES Tj = 25°C to 150°C 1000 V VCGR Tj = 25°C to 150°C; RGE = 1 M fi

Contextual Info: SHEET OF~T E-LDGD HERE SEE EXPLDDED VIEW -15.24— 1.80 TRAVEL f Ï 6.0Û+0.1 Po5. 1 D e s ig n a te P in #1 L D C Q - tio n r 1 0.80 TYP. 1.75 4 2 » 6 9, 8 •, 10 •, 12 •, JJJJJJ -9.3±0.5- 1" 3 * 5 m 7• S * It• CIRCUIT 6 POSITION -1 2 .7 0 - NOTES:

Contextual Info: P g jjjJ G E C P L E S S E Y S E M I C O N D U C T O R S DS3575-3.5 MA28155 RADIATION HARO PROGRAMMABLE PERIPHERAL INTERFACE The MA28155 is a general purpose programmable Input/ O u tp u t d e v ic e d e s ig n e d fo r use w ith th e M AS281 microprocessor. It has 24 I/O pins which may be individually

Contextual Info: SOLDER SUFFIX LF1 CUSTOMER TERMINAL Sn96%, A g4X RoHS LEAD Pb -FREE Yes No RD+ DOT/RECESS LOCATES TERM. #1 .480 REF. [12.19] .600 ?0 1 0 1:1 - RCT - RD- © - RX+ T jjjj CMR JTTT^L % RX- TX+ 1.095 7010 [27.81 ?2 5 ] •© CMT TX- TERM. NO.’s FOR REF. ONLY •

ci cd 3313

Contextual Info: I contact layout Bestückungsplan - bestückt - assemble »e j jjjjjjjjjl'jjjjjjjjjjssr -LLLLLLLLLLj_Li_i_i_i_Li_Li_i3HÜ la CA 2,15 Rn in Paste pii il paste 00 o ' 11.4 Für nicht EP - kompatible Layouts For non pressfit compatible layouts Lochhild für Leiterplatte

09185167903

Abstract: SEK18
Contextual Info: 1 0 , 5 max 10,5 max. E X a ,27 3, 81 m jjjj L n Mit Rechte Vorbehalten/ Ul rights reserved GO 3 9 , 9 max . C o mp o n e n t s i d e 1 E i n l ö t s t i f t e p a s s e n d f ü r L o c h u n g e n 01 ±0. 1 nach IEC 6 0 3 2 6 - 3 Solder pins for PCB connections

1941

Abstract: RADIOTRON rca company Scans-0017341
Contextual Info: IG4-GT/G DETECTOR AMPLIFIER TRIODE F ila m e n t Coated d -c v o l t s V o lt a g e 1.4 C u rre n t 0 .0 5 amo. D ir e c t In t e r e le c t r o d e C a p a c ita n c e s Appr G r id to P la t e jjjjf 2 .3 (jpf G r id t o Filam e nt 2.2 PI a te to F i 1ament

Contextual Info: 4 C31 01 1 5 .7 H O (M r^ 1 2 3 ± 0. 5 -7 * i; ^ (MOUNT I NG D IM E N S IO N S 22 = ^ — 3 (NOTES) 3 .5 C P.C .B . _ o THICKNESS,1 . 6 ’ ± 0 .1 ( TOLERANCE, _C0. 5) ^ T r VS S3 P .C .B O A R D ) ±0.1 5 2. I FO R ±0.1 3 CR3) -6 H O CL \— z jjjjI z

Contextual Info: sJJv o jjjjß vtjojnm/v/ JJJT F y n U i O-ZZ-O 901 V1V0 ON 901VLV0 sionaoad aoisisaa/aoiiovdvo

74ls373 parallel port

Abstract: d92 02 74175 ttl pin diagram 74198 74ls175 pin diagram 74198 ttl 74LS374 D172 D173 9z17
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 F5I Fä| F I jjjjj j j b SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I üü bsJ QNO 9 3 4 5 D85

CY7C1041

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- J M fff I ♦ t t < i¡ / 5; PRELIMINARY *^ ' CY7C1041 256K x 16 Static RAM Features w ritten into th e location spe cifie d on t he ad dre ss pins (Aq throu gh A 1 7 . If byte high en ab le (BHE) is LOW, then da ta from

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM fff I t t ♦ < ij / 5; PRELIMINARY *^ ' CY37032 UltraLogic 32-Macrocell ISR™ CPLD — ts = 3 ns Features — tco = 4 n s • 32 macrocells in two logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: U jjjji R163 051 RM M M M TECH N ICAL C o a x ia l c o n n e c t o r s S T R A I G H T PLUG , CRIMP DATA T Y P E CAB .141 901 Issue : 9034 S E R IE S j N 18 GHz DEP90.R167.500 .512/2 fiats Ccabtes: . H p CHARACTERISTICS NOMINAL IMPEDANCE 50 FREQUENCY RANGE

ERMB22

Contextual Info: Bestückungsplan - contact layout 22 bestückt - assemble 22 JJJJJJJJJJJJJJJJJJj i i i i i i i i i i i i i i i i i ¡1 Für nicht EP - kompatible Layouts For non pressfit compatiUe layouts Lochbild für Leiterplatte {Bestückungsseite 1) 0 0,6 *°.1 Durchmesser des metallisierten Loches

Contextual Info: SO LDER SUFFIX CUSTOM ER TERMINAL R oH S L E A D P b -F R E E LF1 Sn96% , A q 4 % Yes No ioe nrr 1:1 DOT LOCATES TERM. #1 RD+ (T )- .610 ±.015 [15.49 ±.38] T-JJJJ RX+ JïTTTL RD- - RX- 1:1 TD+ @ - 1.135 MAX. [28.83] TX+ liü jJ CTD @ - j^TTTL T D -@ .088 REF. 7

Contextual Info: SHEET OF 4 8 10 IE 14 16 JJJJJJJJ 1* 3* 5* 7* 9 * 11* 13* 15• CIRCUIT 'SHOWN a POS" NOTES: 1. ALL DIMENSIONS IN MM 2 . GENERAL TOLERANCE: X .X = ± 0 .4 X XX—"HO 2 5 3 . TERM. NOS. FOR REFERENCE ONLY. 4 . CONTACT RATINGS: 2 5 m A 24V D C . 5 . MATERIAL (TERMINALS/CONTACTS):

SBO 273

Abstract: hJST TWT Wiring cl100 data
Contextual Info: 5. ELECTRIC CHARACTERISTICS Absolute maximum ratings Ta=25°C Symbol Parameter Power supply voltage Input voltage Test condition -0.5 to +7.0 V AV r e f — 0.5 to V jjjj+ 0 .5 V AVSS -0.5 to +0.5 V V I1 —0.5 to V^^+0.5 V — 0.5 to AVj^gp+0•5 V —0.5 to V jjjj+O .5

KTJ-137

Contextual Info: GSD O iSR / / / // / // / : ER JCA cn 34928 09/14/93 CN 35274 A MJB 01/06/94 j cn I S o m Q >• I O jjjjD. 3 HOLES SS 7s CO I 1.69 MAX. ////// REVISIONS ^ i /// /// ///zzm NOTES: 1. FOR USE WITH RG-9B. 214, k 393/U CABLES. 2. FOR CABLING INSTRUCTIONS SEE CP-480 (3-455).

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JMNK ♦ PRELIMINARY t t *^ ' < ij / 5; CY37064 UltraLogic 64-Macrocell ISR™ CPLD — ts = 4.0 ns Features — tco = 4.0 ns • 64 macrocells in four logic blocks • In-System Reprogrammable™ (ISR™ JTAG-compliant