JEDEC MO-203 AA Search Results

MX23256

Abstract: MX23256-15PC 27256 EPROM 25256 tny 178 tm 1640
Contextual Info: MACRONIX 34Ê INC MX23256/57 D • 5bööööE DDQD17Q 3 .EVI p r e l im in a r y 3 2 ,7 6 8 X 8 STATIC READ ONLY MEMORY T ^ - g - is FEATURES DESCRIPTION . 32,768 X 8-bit organization . Access time - 150 ns max . Current-Operating; 80 mA max Standby: 20 mA max

74hc595n

Abstract: 74HC595M 74hc595w MM74HC595N M74HC595N logic ic 7476 pin diagram
Contextual Info: „ r Revised February 1999 SEMICONDUCTOR TM MM74HC595 8-Bit Shift Registers with Output Latches General Description The M M 74H C 595 high speed shift register utilizes advanced silicon-gate C M OS technology. This device pos­ sesses the high noise im m unity and low pow er consum p­

mcg motor 2232

Abstract: EW 9016 uln 803 ULN 2232 uln 8203 MARK WJ3 voltage regulator ana 609 uln driver circuit yaie ST T4 0560
Contextual Info: Û SPRAGUE PROOF U LN -3 7 5 1 Z T H E M A R K O F R E L IA B IL IT Y Integrated Circuit January 26, 1987 z I CO *>1 in U LN -375 1Z N POWER O PERA TIO N A L AM PLIFIER "U O £ FIATURES • • • • • • • • • o ± 3 V to ± 13 V Operation High Output Sw ing

OMAP 4470

Abstract: TIBPAL22VP10-20C
Contextual Info: TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS013A − D2943, FEBRUARY 1987 − REVISED DECEMBER 2010 • • Choice of Operating Speeds: TIBPAL22VP10-20C . . . 20 ns Max TIBPAL22VP10-25M . . . 25 ns Max

TIBPAL22VP10-20C

Contextual Info: TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS013A − D2943, FEBRUARY 1987 − REVISED DECEMBER 2010 • • • • • • • • • C SUFFIX . . . NT PACKAGE M SUFFIX . . . JT PACKAGE TOP VIEW

Contextual Info: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012A – D3523, JUNE 1990 – REVISED MARCH 1992 • • • • • • • • • • High-Performance Operation: fmax External Feedback . . . 33.3 MHz Propagation Delay . . . 20 ns Max

TIBPAL22VP10-20C

Contextual Info: TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991 • • • • • • • • CLK/I I I I I I I I I I I GND Choice of Operating Speeds: TIBPAL22VP10-20C . . . 20 ns Max

dell

Abstract: TIBPAL22VP10-20C
Contextual Info: TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991 • • • • • • • • CLK/I I I I I I I I I I I GND Choice of Operating Speeds: TIBPAL22VP10-20C . . . 20 ns Max

td 880

Abstract: TIBPAL22VP10-20C
Contextual Info: TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991 • • • • • • • • CLK/I I I I I I I I I I I GND Choice of Operating Speeds: TIBPAL22VP10-20C . . . 20 ns Max

DS040

Abstract: l6232
Contextual Info: PRELIMINARY VF1 FPGA Family BEY O N D PER FO RM AN C E FEATURES AND BENEFITS P u b lic atio n # V F 1003-D S-1 A m en d m en t/O Issu e D ate: N o v e m b e r 1 9 9 8 VF1 FPGA Family ♦ The industry's first Variable-Grain-Architecture enables high-density, high-performance

Contextual Info: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS012A – D3523, JUNE 1990 – REVISED MARCH 1992 • • • • • • • • • • High-Performance Operation: fmax External Feedback . . . 33.3 MHz Propagation Delay . . . 20 ns Max

Contextual Info: TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992 • • • • • • • • • • Choice of Operating Speeds TIBPAL22V10AC . . . 25 ns Max

Contextual Info: TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992 • • • • • • • • • • Choice of Operating Speeds TIBPAL22V10AC . . . 25 ns Max

Contextual Info: TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992 • • • • • • • • • • Choice of Operating Speeds TIBPAL22V10AC . . . 25 ns Max

la 78141

Abstract: INTEGRATE LA 78141 D2920 PAL20L8 PAL20L8A PAL20R4 PAL20R4A PAL20R6A 76785 TIBPAL20R4-25C
Contextual Info: TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS022A − D2920, MAY 1987 − REVISED DECEMBER 2010 • • • TIBPAL20L8’ JT OR NT PACKAGE Low-Power, High-Performance Reduced ICC of 105 mA Max

Contextual Info: TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS SRPS022A − D2920, MAY 1987 − REVISED DECEMBER 2010 • • • • • TIBPAL20L8’ JT OR NT PACKAGE Low-Power, High-Performance Reduced ICC of 105 mA Max

P320S

Abstract: F16V8BQ 16v8b pld program 16R8
Contextual Info: Features * Industry Standard Architecture - Emulates Many 20-pin PALs - Low-cost Easy-to-use Software Tools * High-speed Electrically-erasable Programmable Logic Devices - 7.5 ns Maximum Pin-to-pin Delay * Several Power Saving Options Device lcc, Standby

LA 78141 data

Abstract: 554004
Contextual Info: TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992 • • • • • • • • • • Choice of Operating Speeds TIBPAL22V10AC . . . 25 ns Max

Contextual Info: M i i V VITELIC V53C400 HIGH PERFORMANCE, LOW POWER 4M X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 70/70L 80/80L 10/10L Max. RAS Access Time, tRAC 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA) 35 ns 40 ns 50 ns Min. Fast Page Mode Cycle Time, (tpc)

x1sv

Abstract: 1D10 850C SN74ALVCH16821
Contextual Info: SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037 -J U L Y 1995 DGG OR DL PACKAGE TOP VIEW • Member of the Texas Instruments Widebus Family • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process • ESD Protection Exceeds 2000 V Per

30INT

Abstract: TTL LA 78141 la 78141 pinout "CMOS GATE ARRAY" fuji st zo 607
Contextual Info: TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992 • • • • • • Virtually Zero Standby Power CLK/I I I I I I I I I I I GND Propagation Delay Time: I, I/O to I/O in the Turbo Mode

la 78141 pinout

Contextual Info: TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 JTL AND NT PACKAGE TOP VIEW 24-Pin Advanced CMOS PLD Virtually Zero Standby Power Variable Product Term Distribution Allows

la 78141 pinout

Abstract: KS 5814 LA 78141 data TTL LA 78141 LA 78141 functional diagram TICPAL22V10Z-25CFN TICPAL22V10Z-25CJTL TICPAL22V10Z-25CNT TICPAL22V10Z-30I TICPAL22V10Z-30IFN
Contextual Info: TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992 • • • • • • Virtually Zero Standby Power CLK/I I I I I I I I I I I GND Propagation Delay Time: I, I/O to I/O in the Turbo Mode

Contextual Info: TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D − D3323, SEPTEMBER 1989 − REVISED DECEMBER 2010 • • • • • • . Virtually Zero Standby Power CLK/I I I I I I I I I I I GND Propagation Delay Time: I, I/O to I/O in the Turbo Mode