JEDEC CP 28 Search Results

JEDEC Code

Abstract: JEDEC max1918 package outline weight EIAJ 133-AA JEDEC CP 28 MO133A
Contextual Info: Package Outline Dimensions 24 16.90 17.27 Max 19 18 î n r - in 13 n n n r - ii- in 6 7 0.74 12 Hitachi code JEDEC code EIAJ code Weight g CP-24DB MO-077AA SC-632-A 0.80 9.40 ± 0.25 Hitachi code JEDEC code EIAJ code Weight (g) CP-28DA MO-061 AA SC-637-B

Am29C82

Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •

Am29CB21

Abstract: am29c800 cis 11-pin Am29C821
Contextual Info: Am29C821 / Am29C823 Am29C921 / Am29C923 High-Performance CMOS Bus Interface Registers • • • High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay - 8 ns typical Low standby power JEDEC FCT-compatible specs

amd am2 pinout

Abstract: AM29C821/B3A pinout AM2 AMD CD3024 PD3024 AM29C823 AM29C821PC
Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •

CD3024

Abstract: PD3024 AM29C821PC
Contextual Info: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance C M O S Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs

Contextual Info: cP ÏITSU May 1997 Revision 1.0 SDC4UV7282C- 67/84/100/125 T-S 32MByte (4M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC4UV7282C-(67/84/100/125)T-S is a high performance, 32-megabtye synchronous, dynamic RAM module organized as 4M words by 72 bits, in a 168-pin, JEDEC ECC configuration, dual-in-line memory module (DIMM) package.

4000B

Abstract: 74HC4024 74HC4024D 74HC4024DB 74HC4024N 74HC4024PW
Contextual Info: 74HC4024 7-stage binary ripple counter Product data sheet 1. General description The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A. The 74HC4024 is a 7-stage binary ripple counter with a clock input CP , an overriding

54LS393

Contextual Info: Signetics 54LS393 Counter Dual 4-Bit Binary Ripple Counter Product Specification Military Logic Products FEATURES • Two 4-bit binary counters • Divide-by any binary module up to 28 in one package • Two Master Resets to clear each 4-bit counter individually

74LVC377

Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification Supersedes data of 1998 Jul 29 2004 May 28 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger

823T

Abstract: 825T
Contextual Info: QSFCT821T, 823T, 825T, 2821T, 2823T, 2825T Ö High Speed CMOS Bus Interface 8-, 9-, and 10-Bit Registers QS54/74FCT821T QS54/74FCT823T QS54/74F CT825T QS54/74FCT2821T QS54/74FCT2823T QS54/74FCT2825T FEATURES/BENEFITS • Pin and function compatible to the 74F821/3/5

Contextual Info: 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 8 — 28 November 2011 Product data sheet 1. General description The 74LVC2G74 is a single positive-edge triggered D-type flip-flop with individual data D inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

Contextual Info: 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger Rev. 6 — 28 June 2012 Product data sheet 1. General description The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

Contextual Info: 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger Rev. 5 — 28 November 2011 Product data sheet 1. General description The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

74LVC1G80

Abstract: 74LVC1G80GF 74LVC1G80GM 74LVC1G80GV 74LVC1G80GW
Contextual Info: 74LVC1G80 Single D-type flip-flop; positive-edge trigger Rev. 9 — 28 September 2010 Product data sheet 1. General description The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition

Contextual Info: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 4 — 28 June 2012 Product data sheet 1. General description The 74AUP1G80 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

Contextual Info: 74VHC374 Octal D-Type Flip-Flop with 3-STATE Outputs tm Features General Description • High Speed: tPD = 5.4ns typ at VCC = 5V ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate

74HC299

Abstract: 74HC299D 74HC299DB 74HC299N 74HC299PW 74HCT299 74HCT299D 74HCT299DB JESD22-A114E
Contextual Info: 74HC299; 74HCT299 8-bit universal shift register; 3-state Rev. 03 — 28 July 2008 Product data sheet 1. General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL LSTTL devices. They are specified in

Contextual Info: 74HC299; 74HCT299 8-bit universal shift register; 3-state Rev. 03 — 28 July 2008 Product data sheet 1. General description The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL LSTTL devices. They are specified in

74HC-HCT4094

Abstract: 74hct4094d 74HC4094D 74hct4094 CP/2012
Contextual Info: 74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 5 — 28 June 2012 Product data sheet 1. General description The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC

Contextual Info: 74HC4094; 74HCT4094 8-stage shift-and-store bus register Rev. 5 — 28 June 2012 Product data sheet 1. General description The 74HC4094; 74HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the 4094 of the 4000B series. It is specified in compliance with JEDEC

HEF4094BP

Abstract: HEF4094B HEF4094BT HEF4094BTS SSOP16
Contextual Info: HEF4094B 8-stage shift-and-store bus register Rev. 05 — 28 July 2009 Product data sheet 1. General description The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs

Contextual Info: 74AUP1G74 Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 6 — 28 November 2011 Product data sheet 1. General description The 74AUP1G74 provides a low-power, low-voltage single positive-edge triggered D-type flip-flop with individual data D , clock (CP), set (SD) and reset (RD) inputs and

E 9547

Abstract: digital countdown timer xtr 101 74F525 74F525PC 74F525QC 74F525SC C1995 F525 M28B
Contextual Info: 74F525 Programmable Counter General Description Features The ’F525 is a multi-function 28-pin device It consists of a 16-bit count-down counter logic to control the counter logic to control the state of the outputs and a PLA to decode the particular function selected by the user The list of highspeed timing applications include

Contextual Info: IM P \ P -H n H IE '1 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Mar 18 IC24 Data Handbook Philips Semiconductors 1998 Apr 28 PHILIPS Philips Semiconductors Product specification Dual JR flip-flop with set and reset; positive-edge trigger