J67 PACKAGE Search Results

85003

Abstract: J64 Package
Contextual Info: Package Diagram Plastic Leaded Chip Carriers 20-Lead Plastic Leaded Chip Carrier J61 51-85000-A 28-Lead Plastic Leaded Chip Carrier J64 51-85001-A 1 Package Diagram 32-Lead Plastic Leaded Chip Carrier J65 51-85002-B 44-Lead Plastic Leaded Chip Carrier J67

52-Lead

Abstract: 20 002 32-Lead carrier chip led J69 Package led circuit diagram led datasheets J64 Package
Contextual Info: : Package Diagram Plastic Leaded Chip Carriers 20-Lead Plastic Leaded Chip Carrier J61 28-Lead Plastic Leaded Chip Carrier J64 1 : Package Diagram 32-Lead Plastic Leaded Chip Carrier J65 44-Lead Plastic Leaded Chip Carrier J67 2 : Package Diagram 52-Lead Plastic Leaded Chip Carrier J69

CY7C276-25JC

Abstract: C276 CY7C276 CY7C276-25HC C2761 CY7C276-30JC c2762 C2767
Contextual Info: 1CY 7C27 6 CY7C276 16K x 16 Reprogrammable PROM Features Functional Description • 0.8-micron CMOS for optimum speed/power The CY7C276 is a high-performance 16K-word by 16-bit CMOS PROM. It is available in a 44-pin PLCC/CLCC and a 44-pin LCC packages, and is 100% reprogrammable in windowed packages. The memory cells utilize proven EPROM

J67 Package

Contextual Info: PRELIMINARY CY7C371i UltraLogict 32ĆMacrocell Flash CPLD Device CPLD and is part of the FLASH370it family of highĆdensity, highĆ speed CPLDs. Like all members of the FLASH370i family, the CY7C371i is deĆ signed to bring the ease of use and high performance of the 22V10, as well as PCI

Contextual Info: p yp: v « *1 X X CY7C276 - 16Kx 16 Reprogrammable PROM Features Functional Description • The CY7C276 is a high-performance 16K-word by 16-bit CMOS PROM. It is available in a 44-pin PLCC/CLCC and a 44-pin LCC packages, and is 100% reprogrammable in w in­

7C371-143

Abstract: 7C371-83 7C371L-83 CY7C371 CY7C372 FLASH370 7C371-110
Contextual Info: 7c371: Tuesday, May 26, 1992 Revision: August 9, 1995 CY7C371 UltraLogict 32ĆMacrocell Flash CPLD Features Functional Description D D D The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the FLASH370 family of highĆdenĆ

Contextual Info: PRELIMINARY CYPRESS UltraLogic 32-Macrocell Flash CPLD Device CPLD and is part of the FLASH370i “ family of high-density, high­ speed CPLDs. Like all members of the FLASH370i family, the CY7C371i is de­ signed to bring the ease of use and high performance of the 22V10, as well as PCI

Contextual Info: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

ULTRA37000

Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Features • • • • • • • • • • • designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to

ULTRA37000

Contextual Info: USE ULTRA37000 FOR ALL NEW DESIGNS CY7C371i UltraLogic™ 32-Macrocell Flash CPLD Features • • • • • • • • • • • designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to

C3816

Contextual Info: IIIWI IdlllW. IVIUMUdy, MUyU£>l I / , \ W £ Revision: Wednesday, March 16,1994 CY7C381 CY7C382 W CYPRESS Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: CY7C381P CY7C382P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

l83A

Contextual Info: fax id: 6126 CY7C371 CYPRESS UltraLogic 32-Macrocell Flash CPLD FLASH370 fam ily the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Features • 32 macrocells in two logic blocks • 32 I/O pins The 32 macrocells in the CY7C371 are divided between two

cypress FLASH370

Abstract: 7C371-110 7C371-143 7C371-83 CY7C371 CY7C372 FLASH370
Contextual Info: CY7C371 UltraLogic 32-Macrocell Flash CPLD Features • • • • • • of use and high performance of the 22V10 to high-density CPLDs. 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins Bus Hold capabilities on all I/Os and dedicated inputs

Contextual Info: V CYPRESS CY7C371 UltraLogic 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — Ímax = 143 MHz The CY7C371 is a Flash erasable Complex

u2330

Contextual Info: fax id: 6126 CY7C371 p ro : V « *1 X X - UltraLogic 32-Macrocell Flash CPLD F lash 370 family, the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to high-density CPLDs. Feat ures • 32 m acrocells in two logic blocks The 32 macrocells in the CY7C371 are divided between two

CY7C343B

Abstract: ULTRA37000TM
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C343B 64-Macrocell MAX EPLD Features Functional Description • 64 MAX macrocells in 4 LABs The CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages.

Contextual Info: 71i CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

CY7C343B

Abstract: ULTRA37000TM
Contextual Info: USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C343B 64-Macrocell MAX EPLD Features Functional Description • 64 MAX macrocells in 4 LABs The CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages.

CY7C381P-2JC

Abstract: CY7C381P-2JI vial
Contextual Info: 7C381A: Monday, September 20, 1993 Revision: October 9, 1995 CY7C381P CY7C382P UltraLogict Very High Speed 1K Gate CMOS FPGA Features D Very high speed D D D D D D Ċ Loadable counter frequencies greater than 150 MHz Ċ ChipĆtoĆchip operating frequencies

Contextual Info: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins

LASH370

Contextual Info: fax id: 6136 CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks

frws 5-4

Abstract: CY7C381-0JI C3816 G68 Package vhdl code for lte channel coding CY7C381 CY7C382 7c381 C381-9 C3812
Contextual Info: ¡iiö i id in tJ . iv iu iiu c iy , M u y u t ji i / , Revision: Wednesday, March 16,1994 ¥ CY7C381 CY7C382 cypress Features • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies up to 85 MHz — Input + logic cell + output delays

Contextual Info: CY7C372i UltraLogic 64-Macrocell Flash CPLD Features FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C372i is designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to