J1997 Search Results

Contextual Info: ADVANCE MICRON I 128K TECHNOLOGY, WC. 128Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED, BURST COUNTER AND SINGLE-CYCLE DESELECT FEATURES • • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View

"LCK"

Contextual Info: PRELIMINARY 16 MEG: x16 SDRAM MICRON I TKtHOLMTT, INC. SYNCHRONOUS DRAM MT48LC1M16A1 S - 51 2K x 16 x 2 banks FEATURES • PCIOO-compliant functionality • Fully synchronous; all signals registered on positive edge of system clock • In tern al p ip elin ed operation; colum n ad d ress can be

Contextual Info: 4 MEG X 4 FPM DRAM MICRON I TECHNOLOGY. INC. MT4LC4M4B1, MT4C4M4B1 MT4LC4M4A1, MT4C4M4A1 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • State-of-the-art, high-perform ance, low pow er CMOS silicon-gate process • Single pow er supply +3.3V +0.3V or +5V +10%

Contextual Info: 1 MEG X 4 FPM DRAM MICRON I TECHNOLOGY. INC. DRAM M T4C 4001J FEATURES • 1,024-cycle refresh distributed across 16ms MT4C4001J or 128ms (MT4C4001J L) • Industry-standard pinout, timing, functions and packages • High-performance CMOS silicon-gate process

Contextual Info: |U |IC R O N 4’ 8 MEGx 36 ECC-OPTIMIZED DRAM SIMMs MT9D436 MT18D836 DRAM MODULE FEATURES • Four-CAS#, ECC-optimized configuration in a 72-pin, single in-line memory module SIMM • 16MB (4 Meg x 36) and 32MB (8 Meg x 36) • High-performance CMOS silicon-gate process

9723M

Abstract: Dynamic Memory Refresh Controller
Contextual Info: PRELIMINARY 2 5 6 K x 32 SGRAM MICRON I TECHNOLOGY. INC. SYNCHRONOUS GRAPHICS RAM MT41LC256K32D4 FEATURES • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle

marking 1PC 6-pin

Contextual Info: 1 MEG x 16 EDO DRAM MICRON I TECHNOLOGY. INC. DRAM MT4C1M16E5 MT4LC1M16E5 FEATURES • JEDEC- and industry-standard xl6 timing, functions, pinouts and packages • High-performance CMOS silicon-gate process • Single power supply +3.3V ±0.3V or 5V ±10%

58LC

Contextual Info: ADVANCE MICRON I 64K TECHNOLOGY, N C . 64Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST COUNTER FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View 100-Pin TQFP

X206-1

Contextual Info: ADVANCE |U |IC = R O N 256K X M T58LC256K16/18C5 16/18 SYNCBURST SRAM 256K X 16/ 18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, PIPELINED AND SELECTABLE BURST MODE FEATURES • • • • • • • • • • PIN ASSIGNMENT Top View Fast access times: 4 .5 ,5 , 6 and 7ns

9114s

Contextual Info: ADVANCE MICRON I 256K X TECHNOLOGY, WC. 256Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST COUNTER FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View Fast access times: 4.5, 5, 5.5 an d 6ns

Diagram-64K

Contextual Info: ADVANCE MICRON I 64K TECHNOLOGY, NC. 64Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED, BURST COUNTER AND SINGLE-CYCLE DESELECT FEATURES • • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View

RJ10

Abstract: mobile phone repair FlexPAC 815E E&M interface RJ45 TO 2 BANTAM PLUGS J1996A
Contextual Info: don’t guess… measure it! Agilent Technologies VQT Voice Quality Test Solution Overview and Data Sheet Technology to quickly identify and solve Voice Quality problems in today’s converged IP networks and equipment The Complete Voice Quality Testing Solution

Contextual Info: ADVANCE MICRON I 128K TECHNOLOGY, WC. 128Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST COUNTER FEATURES • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View 100-Pin TQFP

Contextual Info: ADVANCE MICRON I 256K X TECHNOLOGY, WC. 256Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED, BURST COUNTER AND SINGLE-CYCLE DESELECT FEATURES • • • • • • • • • • • • • • • • • • • PIN ASSIGNMENT Top View