ITT S001 Search Results

74C914N

Abstract: 74c914 mm74c914 74C914M
Contextual Info: O ctober 1987 Revised January 1999 SEMICONDUCTOR TM MM74C914 Hex Schmitt Trigger with Extended Input Voltage General Description typ 0.0005V /°C at V qq = 10V . And the hysteresis, V j + - The M M 74C 914 is a m onolithic C M OS Hex S chm itt trig ge r w ith special input protection schem e. This schem e allows

MM74C914N

Abstract: MM74C914M MM74C914 MM74 Fairchild M14A MS-001 N14A
Contextual Info: O ctober 1987 Revised January 1999 S E M IC O N D U C TO R T M MM74C914 Hex Schmitt Trigger with Extended Input Voltage General Description typ 0.0005V /°C at V qq = 10V . And the hysteresis, V j + - T he M M 74C 914 is a m onolithic C M O S Hex Schm itt trig ge r

Contextual Info: Revised D ecem ber 1998 EMICQNDUCTGR tm General Description Features The V H C T 14A is an advanced high speed C M OS Hex Schm itt Inverter fabricated w ith silicon gate C M OS te ch n ol­ ogy. The V H C T 14A contains six independent inverters w hich are capable o f transform ing slow ly changing input

C14SC

Contextual Info: November Revised D ecem ber 1998 S E M IC O N D U C T O R TM 74AC14 Hex Inverter with Schmitt Trigger Input General Description T h e AC 14 contains six inverter gates each w ith a S chm itt trig ge r input. The AC 14 contains six logic inverters w hich accept standard C M OS input signals and provide standard

application of ca3098

Abstract: CA3098 CA3098E MS-001-BA HARRIS SEMICONDUCTOR water level electrical control circuit diagram
Contextual Info: CA3098 January 1999 Programmable schmitt Trigger with Memory, Dual Input Precision Level Detector File Number 896.5 Features • P ro g ra m m a b le O pe ra tin g C u rren t • M icrop ow er S tand by Dissipation T h e C A 3 0 9 8 P ro g ra m m a b le Schm itt Trigger is a monolithic

CA3098E

Abstract: CA3098
Contextual Info: CA3098 January 1999 Programmable schmitt Trigger with Memory, Dual Input Precision Level Detector File Number 896.5 Features • P ro g ra m m a b le O p e ra tin g C u rren t • M icrop ow er S ta n d b y Dissipation T h e C A 3 0 9 8 P ro g ra m m a b le Schm itt Trigger is a m onolithic

Contextual Info: s e m ic o n d u c t o r Revised March 1999 General Description Features The V H C T 14A is an advanced high speed C M OS Hex Schm itt Inverter fabricated w ith silicon gate C M OS te ch n ol­ ogy. The V H C T 14A contains six independent inverters w hich are capable o f transform ing slow ly changing input

Contextual Info: O ctober 1987 Revised January 1999 S E M I C O N D U C T O R TM General Description I Equal source and sink currents I No lim it on input rise and fall tim e T h e C D4093B consists of four S ch m itt-trig ge r circuits. Each circuit functions as a 2-input NAND gate with Schm itttrig ge r action on both inputs. The gate sw itches at different

40106BCN

Abstract: 40106bc 40106B
Contextual Info: O c to b e r 198 7 R e v is e d J a n u a ry 199 9 SEMICONDUCTOR TM General Description Features T h e C D 4 0 1 0 6 B C H ex S c h m itt T rig g e r is a m o n o lith ic c o m - • W id e s u p p ly v o lta g e ra n g e : 3 V to 15 V p le m e n ta ry M O S C M O S in te g ra te d c irc u it c o n s tru c te d

aeg diode Si 61 L

Abstract: aeg diodes D6 SGS Transistors BC23B SILICONIX U315 MZ306 BY126 bcv59 ac128 2N3680
Contextual Info: Semiconductor Data Book Semiconductor Data Book Characteristics of approx. 10 000 Transistors, FETs, UJTs, Diodes, Rectifiers, Optical Semiconductors, Triacs and SCRs, Compiled by A. M. Ball Head of Physics, Teign School Newnes Technical Books Newnes Technical Books

sae 1850 vpw

Abstract: BLIC CDP68HC05 HIP7010 hip7010b J1850 68HC05 68HC11 HIP7010P HIP7020
Contextual Info: Semiconductor H I P 7 1 ADVANCE INFORMATION J1850 Byte Level Interface Circuit August 1996 Features Description • Fully Supports VPW Variable Pulse W idth Messaging Practices of SAE J1850 Standard for Class B Data Com munications Network Interface The Harris HIP7010, J1850 Byte Level Interface Circuit, is a

D4069UBC

Abstract: D4069 74C901 ITT S001 74c914 D4069UB
Contextual Info: A I R C H I L D O ctober 1987 Revised January 1999 SEMICONDUCTOR TM General Description All inputs are protected from dam age due to static dis­ charge by diode clam ps to V DD and V s s- T h e C D4069U B consists of six inverter circuits and is m an­ ufactured using co m plem entary MOS CMOS to achieve

74HC244N

Abstract: 74hc244w
Contextual Info: S eptem ber 1983 Revised February 1999 S E M I C O N D U C T O R TM MM74HC244 Octal 3-STATE Buffer General Description and low pow er consum ption. All three devices have a fanout of 15 LS-TTL equivalent inputs. The M M 74H C 244 is a non-inverting buffer and has tw o

Contextual Info: Revised D ecem ber 1998 SEMICONDUCTOR TM 74 ACT715*74 ACT715-R Programmable Video Sync Generator General Description Four additional signals can also be m ade available w hen C om posite S ync or Blank are used. These signals can be used to generate horizontal or vertical gating pulses, cursor

74HC245AN

Abstract: M74HC245AN MM74HC245A
Contextual Info: A I R C H S eptem ber 1983 I L D Revised February 1999 S E M I C O N D U C T O R TM General Description The M M 74H C 245A 3-STATE bidirectional buffer utilizes advanced silicon-gate C M OS technology, and is intended fo r tw o-w ay asynchronous com m unication between data

Contextual Info: Revised O ctober 1998 74AC08 • 74ACT08 Quad 2-Input AND Gate General Description Features T h e A C /AC T08 contains four, 2 -input AN D gates. • Ice reduced by 50% on 74A C only ■ O utputs source/sink 24 mA Ordering Code: Order Number Package Number

HC14M

Abstract: 74VHC14A
Contextual Info: s e m ic o n d u c t o r R e v is e d A p ril 199 9 a g e . T h is d e v ic e c a n be u s e d to in te rfa c e 5 V to 3 V s y s te m s General Description The VH C 14 is an advanced a n d tw o s u p p ly s y s te m s s u c h a s b a tte ry b a c k up . T h is c ir ­

D4040BC

Abstract: D4020BC D4040
Contextual Info: Revised January 1999 EMICQNDUCTGR tm CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters 12-Stage Ripple Carry Binary Counters 14-Stage Ripple Carry Binary Counters General Description Features The C D4020BC , C D4060BC are 14-stage ripple carry

Contextual Info: A I R C H S eptem ber 1983 I L D Revised February 1999 S E M IC O N D U C T O R TM General Description The M M 74H C 221A high speed m onostable m ultivibrators one shots utilize advanced silicon-gate C M OS te ch n ol­ ogy. T h e y feature speeds com parable to low pow er Schottky TT L circuitry w hile retaining the low pow er and high

Contextual Info: R e v is e d F e b ru a ry 1999 s e m ic o n d u c t o r MM74HCU04 Hex Inverter General Description a re p ro te c te d fro m d a m a g e d u e to s ta tic d is c h a rg e b y in te r­ nal d io d e c la m p s to V q q a n d g ro u n d . T h e M M 7 4 H C U 0 4 in v e rte rs u tiliz e a d v a n c e d s ilic o n -g a te

Contextual Info: Revised D ecem ber 1998 SEMICONDUCTOR TM 74ACTQ14 Quiet Series Hex Inverter with Schmitt Trigger Input General Description The AC TQ 14 utilizes Fairchild Q u iet Series™ Technology to guarantee quiet output sw itching and im prove dynam ic threshold perform ance. FACT Q u iet Series™ features

ATIC 164 D2

Abstract: ATIC 164 D2 48 pin ATIC 164 D3 ATIC 107 ATIC 164 D2 44 pin atic 139 ATIC 164 ATIC 71 b1 YF04 AO122
Contextual Info: FG7000 SERIES DATABOOK 1999 FG73A_B HOLTEK SEMICONDUCTOR INC. TABLE OF CONTENTS Chapter 1 Introduction to HOLTEK FG73A-B GATE A R R A Y . 1-1 1.0FS7000 S e r i e s . 1-1

Contextual Info: 74AC74 • 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description A synchronous Inputs: The A C /AC T74 is a dual D-type flip-flop with Asynchronous C lear and S e t inputs and com plem entary Q, Q outputs. Inform ation at the input is transferred to the outputs on the

CX20187

Abstract: MM74HC423AM 74hc423a 74HC M16A M16D MM74HC423A MM74HC423AMTC MM74HC423ASJ MTC16
Contextual Info: Revised February 1999 E M IC O N D U C T G R T M General Description T he 7 4H C 423A high speed m onostable m ultivibrators one shots utilize advanced silicon-gate C M O S technology. T h e y feature speeds com parable to low pow er Schottky T T L circuitry w hile retaining the low pow er and high noise