IP CORE Search Results

lte turbo encoder

Abstract: its 31567 data sheet xilinx lte TURBO decoder XTP025 LDPC encoder decoder ip core LDPC decoder ip core 24604 LTE DL Channel Encoder 25160 dvb-s encoder design with fpga
Contextual Info: 30 IP Release Notes Guide XTP025 v1.6 June 24, 2009 Xilinx Intellectual Property (IP) cores including LogiCORE IP cores are delivered through software updates available from the Xilinx Download Center. The latest versions of IP products have been tested and are delivered with the current IP

LDPC decoder ip core

Abstract: 33258 24604 lte turbo encoder LDPC decoder timing 3GPP LTE MIMO Decoder XTP025 223-28 LDPC encoder 1000BASE-X
Contextual Info: 31 IP Release Notes Guide XTP025 v1.8 December 2, 2009 Xilinx Intellectual Property (IP) cores including LogiCORE IP cores are delivered through software updates available from the Xilinx Download Center. The latest versions of IP products have been tested and are delivered with the current IP

Contextual Info: IP Suites Page 1 of 3 Home > About Us > Newsletters > LatticeNEWS November 2008 > IP Suites November 2008 IP Suites Offer a Total IP Solution for Less Lattice's selection of bundled IP cores provide designers with greater flexibility at a reduced cost. Traditionally, Intellectual Property IP cores are licensed for a specific endproduct. This approach works well if you have a specific project that needs a

CEA-861-D

Abstract: cea-861d displayport receiver 1.2 IEC61937 displayport 1.1a DisplayPort 1.3 Analogix IEC-61937 video transmitter module Analogix AN
Contextual Info: Product Brief DisplayPort 1.1a Transmitter IP Core DisplayPort 1.1a Transmitter IP Core The DisplayPort Transmitter IP core is fully compliant with DisplayPort 1.1a with HDCP content protection specifications. The IP core provides all the signal requirements for the DisplayPort

AMBA AXI4 stream specifications

Abstract: state machine axi 3 protocol state machine axi Xilinx ISE Design Suite
Contextual Info: LogiCORE IP AXI Slave Burst v1.00b DS769 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Slave Burst core provides an interface between the AXI4 memory-mapped interface and the IP interconnect interface. This core is designed

Contextual Info: White Paper Simulating Visual IP Models with the ModelSim Simulator for PCs You can use the Visual IP software from Innoveda with Altera-provided models to simulate Altera intellectual property IP cores in third-party VHDL and Verilog HDL simulators. The following simulators support Visual IP

RGB to CSI-2

Abstract: CAMERA PARALLEL RGB TO MIPI CSI-2 Camera Module CSI2 MIPI csi-2 SpeedTags CMOS Camera Module CSI RGB TO MIPI cSI2 MIPI TO bt 601 MIPI csi 5 MP camera module 2 MP
Contextual Info: IP Product Brief Applications • Mobile Phones • Portable Media camerIC - 18 IP core Players Camera Processor IP Cores up to 18 Megapixels • Netbook PCs • CMOS Sensor Module The camerIC-18 camera processor IP cores are a complete 18 megapixel MP video and still

shiftreg16

Abstract: ispLEVER project Navigator Maximum Megahertz Project ispLEVER project Navigator route place vhdl code for character display
Contextual Info: ispLEVER Tutorials Generating Parameterized Modules and IP Cores Table of Contents Generating Parameterized Modules and IP Module 1: Verilog HDL Design with LPMs Using the Module/IP Manager .4

d5200c

Abstract: RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1
Contextual Info: LogiCORE IP AXI Block RAM BRAM Controller (v1.03a) DS777 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite, Embedded Development Kit

vhdl code for rotation cordic

Abstract: DS858 LogiCORE IP CORDIC CORDIC divider CORDIC in xilinx cordic design for fixed angle rotation CORDIC v5.0 CORDIC v4.0 XC7K325T CORDIC system generator xilinx
Contextual Info: LogiCORE IP CORDIC v5.0 DS858 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP v5.0 core implements a generalized coordinate rotational digital computer CORDIC algorithm. Features Core Specifics Supported

TUTORIALS xilinx FFT

Abstract: 16 QAM modulation verilog code Xilinx usb2 cable Schematic Xilinx usb cable Schematic qpsk implementation using verilog xilinx mp3 vhdl decoder CODE VHDL TO ISA BUS INTERFACE FPGA based dma controller using vhdl VHDL code of DCT by MAC VHDL CODE FOR HDLC controller
Contextual Info: White Paper: Spartan-II R WP137 v1.0 March 21, 2001 Summary Intellectual Property (IP) Cores for Home Networking Author: Amit Dhir Spartan -II FPGAs, programmed with IP cores, enable home networking products. Xilinx develops IP cores and partners with third-party IP providers to provide customers with a suite

Contextual Info: White Paper Simulating Visual IP Models with the NC-Verilog, Verilog-XL, VCS, or ModelSim UNIX Simulators You can use the Visual IP software from Innoveda with Altera-provided models to simulate Altera intellectual property (IP) cores in third-party VHDL and Verilog HDL simulators. The following simulators support Visual IP

vending machine using microcontroller

Abstract: pinout rs232 to rj45
Contextual Info: SocketEthernet IP Embedded Serial-to-Ethernet Device Server Benefits • IP-enable virtually any serial device • Flexible IP protocol stack • Universal socket connectivity The SocketEthernet IP® device server connects serial devices to an IP network for remote monitoring, control

Contextual Info: LogiCORE IP AXI INTC v1.03a DS747 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single

Contextual Info: LogiCORE IP ChipScope Pro IBERT for 7 Series GTH Transceivers v2.01a DS873 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The customizable LogiCORE IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series

ET1100 Sample Schematic

Abstract: et1100 ET1200 verilog disadvantages spi slave ethercat ET1815 ET1100 SPI vhdl ethercat marking code Bi vhdl code for TRAFFIC LIGHT CONTROLLER 4 WAY
Contextual Info: Hardware Data Sheet ET1815 / ET1817 Slave Controller IP Core for Xilinx FPGAs IP Core Release 2.02a Section I – EtherCAT Slave Controller Technology Section II – EtherCAT Slave Controller Register Description Section III – EtherCAT IP Core Description: Installation, Configuration,

XC7VH580T-HCG1155-2

Abstract: prbs pattern generator using vhdl verilog prbs generator ibert XC7VH580T ChipScope IBERT
Contextual Info: v LogiCORE IP ChipScope Pro IBERT for 7 Series GTZ Transceivers v2.0 DS878 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The customizable LogiCORE IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series

xc6slx75-3

Abstract: rtl not XC7K410T XC6SLX75 fgg676 AMBA AXI specifications kintex 7
Contextual Info: LogiCORE IP AXI INTC v1.02a DS747 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the

uart vhdl

Abstract: XC5VLX50-FF676
Contextual Info: LogiCORE IP XPS SYSMON ADC v3.00.b DS620 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Platform Studio (XPS) System Monitor (SYSMON) Analog-to-Digital Converter (ADC) Intellectual Property (IP) core is a 32-bit slave

Polyphase Filter Banks

Abstract: non integer rate sampling rate converter verilog XC6SLX150-2FGG484 fir compiler v4 how example make fir filter in spartan 3 vhdl direct-form FIR Filter verilog polyphase system generator matlab ise Harris Microwave Semiconductor Division DS534 DSP48
Contextual Info: IP LogiCORE FIR Compiler v5.0 DS534 March 1, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR filters

verilog code for dual port ram with axi interface

Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
Contextual Info: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories

Xilinx Spartan-6 LX4

Abstract: DS817 spartan6 jtag instruction spartan 6 LX150 fifo generator xilinx spartan state machine axi axi crossbar Xilinx Spartan 6 LX75 icape2 state machine axi 3 protocol
Contextual Info: LogiCORE IP AXI HWICAP v2.02.a DS817 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Advanced eXtensible Interface (AXI) HWICAP (Hardware Internal Configuration Access Port) core for the AXI Interface

Contextual Info: LogiCORE IP AXI INTC v1.04a DS747 June 19, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Interrupt Controller (AXI INTC) core receives multiple interrupt inputs from peripheral devices and merges them to a single

verilog code for fir filter using DA

Abstract: vhdl code for FFT 4096 point P6421 p4826 vhdl code for radix 2-2 parallel FFT 16 point FIR FILTER implementation on fpga VHDL code for polyphase decimation filter FDATOOL DSP48 spartan 6 VHDL code for polyphase decimation filter using D
Contextual Info: LogiCORE IP FIR Compiler v6.3 DS795 October 19, 2011 Product Specification Overview LogiCORE IP Facts The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable, area-efficient high-performance FIR