IO1R Search Results

ixys cs 45-16 io1r

Abstract: CS 110 thyristor
Contextual Info: CS 45 Phase Control Thyristor VRRM = 800-1600 V 75 A IT RMS = IT(AV)M = 48 A VRSM VRRM VDSM VDRM V V Type 900 800 CS 45-08 io1 1300 1200 CS 45-12 io1 1700 1600 CS 45-16 io1 CS 45-16 io1R A C TO-247 AD ISOPLUS247TM Version io1 Version io1R C A G G h A (TAB)

ixys cs 45-16 io1r

Contextual Info: CS 45 Phase Control Thyristor VRRM = 800-1600 V 75 A IT RMS = IT(AV)M = 48 A VRSM VRRM VDSM VDRM V V Type 900 800 CS 45-08 io1 1300 1200 CS 45-12 io1 1700 1600 CS 45-16 io1 CS 45-16 io1R A C TO-247 AD ISOPLUS247TM Version io1 Version io1R C A G G h A (TAB)

Contextual Info: CS 45 VRRM = 800-1600 V 75 A IT RMS = IT(AV)M = 48 A Phase Control Thyristor VRSM VRRM VDSM VDRM V V Type 900 800 CS 45-08 io1 1300 1200 CS 45-12 io1 1700 1600 CS 45-16 io1 CS 45-16 io1R A C TO-247 AD ISOPLUS247TM Version io1 Version io1R C A G G h A (TAB)

M48A

Abstract: 2100IG
Contextual Info: CS 45 Phase Control Thyristor VRRM = 800-1600 V IT RMS = 75 A IT(AV)M = 48 A VRSM VRRM VDSM VDRM V V Type 900 800 CS 45-08 io1 1300 1200 CS 45-12 io1 1700 1600 CS 45-16 io1 CS 45-16 io1R A C TO-247 AD ISOPLUS247TM Version io1 Version io1R C A G G h A (TAB)

Contextual Info: CYDM064B16 CYDM128B16 CYDM256B16 1.8 V 4 K/8 K/16 K x 16 MoBL Dual-Port Static RAM 1.8V 4K/8K/16K x 16 MoBL® Dual-Port Static RAM Features • True dual ported memory cells that allow simultaneous access of the same memory location ■ Expandable data bus to 32-bits with Master or Slave chip select

70v3319s133

Abstract: 70V3319 A12L IDT70V3319 IDT70V3319S 70V3319S 70V3319PRF
Contextual Info: HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3319S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

Contextual Info: CY7C024AV/024BV/025AV/026AV 3.3 V 4 K / 8 K / 16 K x 16 Dual-Port Static RAM 3.3 V 4 K / 8 K / 16 K × 16 Dual-Port Static RAM Features • Automatic power down ■ True dual-ported memory cells which enable simultaneous access of the same memory location

70V3319

Abstract: A12L IDT70V3319 IDT70V3319S L1 ORT X
Contextual Info: HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3319S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

IDT70V3399

Contextual Info: HIGH-SPEED 3.3V 256/128K x 18 IDT70V3319/99S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Š Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.6ns 166MHz /4.2ns (133MHz) (max.)

026AV

Abstract: CYPRESS CROSS REFERENCE dual port sram CY7C024AV-15AI 9l reset CY7C036AV cy7c026av-20axi IO0R-IO17R
Contextual Info: CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • True dual-ported memory cells which enable simultaneous access of the same memory location ■ 4, 8 or 16K x 16 organization ■ CY7C024AV/024BV [1]/ 025AV/026AV

TSC695f user

Abstract: sparc v7 ERC32 TSC695 TSC695F
Contextual Info: Rad. Hard 32-bit SPARC Embedded Processor User Guide Table of Contents Section 1 Features. 1-1 1.1 1.2 1.3 1.4 Description .1-2

Contextual Info: HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3319S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access

SEM t11

Abstract: A12L A13L IDT70V639 IDT70V639S 70V639S10
Contextual Info: PRELIMINARY IDT70V639S HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns max.

4833

Abstract: 70V3379 A12L A13L A14L IDT70V3379 IDT70V3379S
Contextual Info: HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns max.

Contextual Info: CYDM064B16 CYDM128B16 CYDM256B16 MoBL 1.8V 4K/8K/16K x 16 Dual-Port Static RAM 1.8V 4K/8K/16K x 16 MoBL® Dual-Port Static RAM Features • True dual ported memory cells that allow simultaneous access of the same memory location ■ Expandable data bus to 32-bits with Master or Slave chip select

Epcos n67 material

Abstract: 1000uF 25V capacitor str 5 q 0765 POWER SUPPLY CIRCUIT ICE2B265 equivalent AN-SMPS-ICE2AXXX-1 EPCOS n67 ICE2B265 SFH617-3 ICE2B265 Application Note 500 WATT smps
Contextual Info: Version 1.0 , September 2001 Design Note DN-SMPS Singlestage CoolSET Design of 30W Off-Line SMPS using CoolSET ICE2B265 Authors: Yew Ming Lik Junyang Luo Meng Kiat Jeoh Published by Infineon Technologies AG http://www.infineon.com Power Management & Supply

CY7C036AV

Contextual Info: CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Features • True dual-ported memory cells which enable simultaneous access of the same memory location ■ Fully asynchronous operation ■ Automatic power down

Contextual Info: HIGH-SPEED 3.3V 256/128K x 18 IDT70V3319/99S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Š Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.6ns 166MHz /4.2ns (133MHz) (max.)

Contextual Info: Š HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns max.

4833

Abstract: 70V3379 A12L A13L A14L IDT70V3379 IDT70V3379S 70V3379BF
Contextual Info: HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V I/O Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns max.

A12L

Abstract: A13L A14L A15L IDT70V3389 IDT70V3389S
Contextual Info: HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 5/6ns max. Pipelined output mode

4833

Abstract: 70V3379 A12L A13L A14L IDT70V3379 IDT70V3379S
Contextual Info: Š HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns max.

mec oscillator

Abstract: erc32 trap ERC32 2M x 16 DPRAM TSC691E TSC692E TSC693E
Contextual Info: TSC693E TSC693E Memory Controller User's Manual For Embedded Real time 32-bit Computer ERC32 for SPACE Applications MATRA MHS Rev. D (10 Apr. 97) 1 TSC693E TABLE OF CONTENTS Page 1. 1.1. 1.2. 1.2.1. 1.2.2. 1.3. 1.4. 1.4.1. 1.4.2. 1.4.3. INTRODUCTION . 4

5622

Contextual Info: HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM IDT70V631S Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns max. – Industrial: 12ns (max.)