INTEGER ARITHMETIC Search Results

INTEGER ARITHMETIC Equivalents

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INTEGER ARITHMETIC Result Highlights (4)

Part	Manufacturer	Description
SN54LS181J	Texas Instruments	Arithmetic Logic Units/Function Generators 24-CDIP -55 to 125
SNJ54LS181J	Texas Instruments	Arithmetic Logic Units/Function Generators 24-CDIP -55 to 125
JM38510/07801BJA	Texas Instruments	Arithmetic Logic Units/Function Generators 24-CDIP -55 to 125
M38510/07801BJA	Texas Instruments	Arithmetic Logic Units/Function Generators 24-CDIP -55 to 125

INTEGER ARITHMETIC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
booth multiplier code in vhdl Abstract: vhdl code for Booth multiplier verilog code pipeline square root 4-bit AHDL adder subtractor 7,4 bit hamming decoder by vhdl 3 bit booth multiplier using verilog code low pass fir Filter VHDL code vhdl code for 4 bit updown counter multiplier accumulator MAC code VHDL algorithm vhdl code for a updown counter Contextual Info: Integer Arithmetic Megafunctions User Guide July 2010 UG-01063-2.0 The Altera integer arithmetic megafunctions offer you the convenience of performing mathematical operations on FPGAs through parameterizable functions that are optimized for Altera device architectures. These functions offer efficient logic	Original	UG-01063-2 booth multiplier code in vhdl vhdl code for Booth multiplier verilog code pipeline square root 4-bit AHDL adder subtractor 7,4 bit hamming decoder by vhdl 3 bit booth multiplier using verilog code low pass fir Filter VHDL code vhdl code for 4 bit updown counter multiplier accumulator MAC code VHDL algorithm vhdl code for a updown counter	PDF
8 bit left right shift register Abstract: MCF5200 PC111 Contextual Info: SECTION 4 INTEGER INSTRUCTIONS This section describes the integer instructions for the ColdFire Family. A detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic. MOTOROLA MCF5200 FAMILY PROGRAMMER’S REFERENCE MANUAL	OCR Scan	MCF5200 8 bit left right shift register PC111	PDF
wavelet transform Abstract: wavelet power system TMS320C40 abstract on RTOS and multitasking Daubechies filter integer "frame grabber" Contextual Info: DSPS Fest ’99 An Integer Wavelet Transform, Implemented on a Parallel TI TMS320C40 Platform Page 1 AN INTEGER WAVELET TRANSFORM, IMPLEMENTED ON A PARALLEL TI TMS320C40 PLATFORM Francis Decroos1,2, Peter Schelkens1,2, Gauthier Lafruit2, Jan Cornelis1, Francky Catthoor2,3	Original	TMS320C40 B-1050 B-3001 Shap93] SPRU96] TMS320C40 Swel95] Thre95] wavelet transform wavelet power system abstract on RTOS and multitasking Daubechies filter integer "frame grabber"	PDF
M68000 Abstract: M68040 MC68000 MC68008 MC68010 MC68040 MC68EC040 Contextual Info: SECTION 2 INTEGER UNIT This section describes the organization of the M68040 integer unit IU and presents a brief description of the associated registers. Refer to Section 3 Memory Management Unit (Except MC68EC040 and MC68EC040V) for details concerning the memory	OCR Scan	M68040 MC68EC040 MC68EC040V) MC68040 32-bit M68000 MC68000 MC68008 MC68010	PDF
RM5260 Abstract: CQFP 208 Contextual Info: ACT5260 64-Bit Superscaler Microprocessor Features • ■ ■ ■ Full militarized QED RM5260 microprocessor Dual Issue superscalar QED RISCMark - can issue one integer and one floating-point instruction per cycle microprocessor - can issue one integer and one	Original	ACT5260 64-Bit RM5260 150MHz 200MHz SPECInt95 SPECfp95 R4600, R4700 R5000 CQFP 208	PDF
CQFP 208 datasheet Abstract: ACT5260 R4000 R4700 R5000 Contextual Info: ACT5260 64-Bit Superscaler Microprocessor Features • ■ ■ ■ Full militarized QED RM5260 microprocessor Dual Issue superscalar QED RISCMark - can issue one integer and one floating-point instruction per cycle microprocessor - can issue one integer and one	Original	ACT5260 64-Bit RM5260 150MHz 200MHz SPECInt95 SPECfp95 R4600, R4700 R5000 CQFP 208 datasheet ACT5260 R4000 R5000	PDF
Contextual Info: OR&ON EMBEDDED 64-BIT ORION RISC MICROPROCESSOR FEATURES • High-performance embedded 64-bit microprocessor - 64-bit integer operations - 64-bit registers - 80MHz, 100MHz, 133MHz operation frequency • High-performance DSP capability - 66.7 Million Integer Multiply-Accumulate Operations/	OCR Scan	64-BIT 80MHz, 100MHz, 133MHz 133MHz	PDF
vhdl code of floating point unit Abstract: ieee floating point vhdl digital clock verilog code APEX20K APEX20KC APEX20KE FLEX10KE ieee floating point verilog Contextual Info: DFP2INT Floating Point To Integer Pipelined Converter ver 2.20 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 standard. DFP2INT supports single precision real numbers and double word integers 4	Original	IEEE-754 APEX20K APEX20KE APEX20KC vhdl code of floating point unit ieee floating point vhdl digital clock verilog code APEX20K APEX20KC APEX20KE FLEX10KE ieee floating point verilog	PDF
AN-603 Abstract: C1995 integer arithmetic A01B Contextual Info: National Semiconductor Application Note 603 Raj Gopalan July 1989 This report describes the implementation of signed integer arithmetic operations on the HPC HPC hardware support for unsigned arithmetic operation In order to support signed integer arithmetic operations on the HPC the user can represent negative numbers in two’s complement form and	Original	16-bit 32-bit 20-3A AN-603 C1995 integer arithmetic A01B	PDF
verilog code for floating point unit Abstract: ieee floating point vhdl vhdl code for digital clock vhdl code of floating point unit ieee floating point verilog Contextual Info: Integer to Floating Point Pipelined Converter ver 2.31 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 standard. DINT2FP supports double word integers 4 Bytes and single precision real	Original	IEEE-754 IEEE-754 verilog code for floating point unit ieee floating point vhdl vhdl code for digital clock vhdl code of floating point unit ieee floating point verilog	PDF
ieee floating point vhdl Abstract: floating point verilog ieee floating point verilog APEX20K APEX20KC APEX20KE FLEX10KE IEEE-754 Contextual Info: DINT2FP Integer to Floating Point Pipelined Converter ver 2.32 OVERVIEW The DINT2FP is the pipelined integer to floating point converter. The input and output numbers format is according to IEEE-754 standard. DINT2FP supports double word integers 4 Bytes and single precision real	Original	IEEE-754 IEEE-754 FLEX10KE APEX20K APEX20KE APEX20KC ieee floating point vhdl floating point verilog ieee floating point verilog APEX20K APEX20KC APEX20KE FLEX10KE	PDF
verilog code for floating point unit Abstract: ieee floating point verilog digital clock vhdl code vhdl code of floating point unit floating point verilog Contextual Info: Floating Point To Integer Pipelined Converter ver 2.07 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 standard. DFP2INT supports single precision real numbers and double word integers 4	Original	IEEE-754 IEEE-754 verilog code for floating point unit ieee floating point verilog digital clock vhdl code vhdl code of floating point unit floating point verilog	PDF
MSP430 General Purpose Subroutines Abstract: MSP430 T001 T010 T011 T101 T110 FPP04 TMS320C5x random noise generator complet RF sensor Contextual Info: Chapter 5 Software Applications 5-1 5.1 Integer Calculation Subroutines Integer routines have important advantages compared to all other calculation subroutines: - Speed: Highest speed is possible especially when no loops are used - ROM space: Least amount of ROM space is needed for these subroutines	Original	MSP430 MSP430 General Purpose Subroutines T001 T010 T011 T101 T110 FPP04 TMS320C5x random noise generator complet RF sensor	PDF
Contextual Info: LOW-COST EMBEDDED ORION RISC MICROPROCESSOR FEATURES • High-performance embedded 64-bit microprocessor - 64-bit integer operations - 64-bit registers - 100MHz, 133MHz, 150 MHz and 180MHz operation frequency • High-performance DSP capability - 75 Million Integer Multiply-Accumulate Operations/sec	OCR Scan	64-bit 100MHz, 133MHz, 180MHz 180MHz 150MHz 133MHz	PDF

TA 7136 p Abstract: weitek 7137-100-G ad 7137 Contextual Info: WTL 7137 32-BIT INTEGER PROCESSOR ADVANCE DATA Features 32-BIT, SINGLE-CHIP PROCESSOR o 3 2-bit Integer ALU o 4-port 36x32 Register File o Parallel Multiply/Divide Unit o 32-bit Shift/Field Merge Unit POWERFUL INSTRUCTION SET o Add, Subtract, Multiply, Divide	OCR Scan	32-BIT 32-BIT, 36x32 144-pin 120ns 100ns 7137-120-G 7137-100-G TA 7136 p weitek ad 7137	PDF
Contextual Info: in te l CHAPTER 7 FLOATING-POINT UNIT The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floating point processing algorithms and exception handling architecture defined in the IEEE 754 and	OCR Scan	01fl070fl	PDF
DSP56000 Contextual Info: SECTION 3 Direct Table Look-Up “When fractional values of delta are used, samples of points between table entries must be estimated using the table values.” 3.1 Integer Delta Implementation This implementation is a direct table look-up method with delta being a positive integer number. Because	Original		PDF
weitek Abstract: P11000 ta 7136 AD27 AD29 AD30 32-bit-Integer weitek 7137 weitek 7136 TA 7136 p Contextual Info: WTL 7137 32-BIT INTEGER PROCESSOR ADVANCE DATA APRIL, 1986 Features 32-BIT, SINGLE-CHIP PROCESSOR o 3 2-bit Integer ALU o 4-port 36x32 Register File o Parallel Multiply/Divide Unit o 32-bit Shift/Field Merge Unit POWERFUL INSTRUCTION SET o Add, Subtract, Multiply, Divide	OCR Scan	32-BIT 32-BIT, 36x32 144-pin 120ns 7137-120-GCD 100ns 7137-100-GCD weitek P11000 ta 7136 AD27 AD29 AD30 32-bit-Integer weitek 7137 weitek 7136 TA 7136 p	PDF
L64801 Abstract: hal 2810 Contextual Info: Chapter 2 L64801 Integer Unit This chapter provides a description o f the L64801 Integer Unit, also referred to as the IU. The topics in this chapter include: 2.1 General Description • General Description page 2-1 ■ Internal Registers (page 2-2) ■	OCR Scan	L64801 32-bit L64301179-pinCPGA hal 2810	PDF
intel 8087 architecture Abstract: sahf instruction intel 8086 Arithmetic and Logic Unit -ALU 8087 coprocessor architecture 8086 instruction set 8086 opcode sheet free binary numbers multiplication 8088 instruction set intel 8086 opcode sheet procedure for converting to opcodes in 8086 Contextual Info: Floating-Point Unit 31 The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floatingpoint processing algorithms and exception handling architecture defined in the IEEE 754 and 854	Original		PDF
hal 2810 Contextual Info: Chapter 2 L64801 Integer Unit This chapter provides a description o f the L64801 Integer Unit, also referred to as the IU. The topics in this chapter include: 2.1 General Description • General Description page 2-1 ■ Internal Registers (page 2-2) ■	OCR Scan	L64801 hal 2810	PDF
aaa instruction Abstract: pentium instruction set CMPXCHG Pentium Processor Family sahf instruction "vector instructions" saturation SA01-FE-3092-3 FLOW ELEMENT Contextual Info: Instruction Set Summary 30 This chapter lists all the instructions in the Intel Architecture instruction set, divided into three functional groups: integer, floating-point, and system. It also briefly describes each of the integer instructions. Brief descriptions of the floating-point instructions are given in “Floating-Point Unit”; brief	Original		PDF
AKT01 Abstract: Decimal Integer Output Subroutines MSP430 General Purpose Subroutines MSP430 T001 T010 T011 T101 T110 CNV04 Contextual Info: Chapter 5 Software Applications Topic Page 5.1 Integer Calculation Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 Table Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32	Original	16-bit, 32-bit, 40-bit BIN16 16-bit 16-bit 08000h 07FFFh) AKT01 Decimal Integer Output Subroutines MSP430 General Purpose Subroutines MSP430 T001 T010 T011 T101 T110 CNV04	PDF
16 BIT ALU design structural Contextual Info: Chapter 2 TurboSPARC Architecture 2.1 INTEGER UNIT AND FLOATING POINT CONTROLLER The integer unit IU and floating point control (FPC) are merged into a 9-stage pipeline. Below are some of the features of the IUFPC. • 9 stage instruction pipeline. • No branch folding. Branch instructions (taken/non-taken) execute in one cycle.	Original		PDF

INTEGER ARITHMETIC Search Results

INTEGER ARITHMETIC Equivalents

INTEGER ARITHMETIC Result Highlights (4)

INTEGER ARITHMETIC Datasheets Context Search

booth multiplier code in vhdl

8 bit left right shift register

wavelet transform

M68000

RM5260

CQFP 208 datasheet

vhdl code of floating point unit

AN-603

verilog code for floating point unit

ieee floating point vhdl

verilog code for floating point unit

MSP430 General Purpose Subroutines

TA 7136 p

DSP56000

weitek

L64801

intel 8087 architecture

hal 2810

aaa instruction

AKT01

16 BIT ALU design structural