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INICORE Datasheets (7)

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Part	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CANaccess	Inicore	CAN2.0B on FPGA	Original	PDF	49.41KB	14
iAH-INTC32	Inicore	AMBA (AHB) compliant, fully programmable interrupt controller with 32 interrupt sources.	Original	PDF	46.34KB	11
iAH-LCDC	Inicore	LCD controller	Original	PDF	37.49KB	7
iAP-CAN16f	Inicore	full CAN controller	Original	PDF	47.85KB	14
iniADPLL	Inicore	All Digital Phase Locked Loop	Original	PDF	24.2KB	5
iniCAN-Observer	Inicore	data link layer observer	Original	PDF	32.94KB	7
iniFUART	Inicore	Fast Universal Asynchronous Receiver Transmitter (FUART)	Original	PDF	39.13KB	7

INICORE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: iniUTOPIA RX/TX and Inicore, a CoreHDL Partner Asynchronous Transfer Mode ATM Interface Features • • • • • • • • • • • General Description UTOPIA is a common interface in Asynchronous Transfer Mode (ATM) subsystems defined by the ATM Forum. The iniUTOPIA core	Original	16-bit 5172125-0f	PDF
alarm clock verilog code Abstract: automatic alarm verilog code Contextual Info: Datasheet RTC MODULE Version 1.0.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2003 INICORE INC. RTCmodule Datasheet Table of Contents 1	Original	alarm clock verilog code automatic alarm verilog code	PDF
RTSX72S Abstract: A24D16 vmebus vhdl vhdl code for door vme bus interface verilog APA150 BU D16 vmebus controller vhdl testbench code vhdl synchronous parallel bus SX32A-3 Contextual Info: Optimized for VME A24D16 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME	Original	a24d16 1-199cess sept/2003 rtsx72s +8vmebus vhdl vhdl code for door vme bus interface verilog apa150 bu d16 vmebus controller vhdl testbench code vhdl synchronous parallel bus sx32a-3	PDF
vhdl code for door Abstract: RTSX72 vhdl synchronous parallel bus APA600 VME64 interrupt controller verilog code interrupt controller verilog 656 fpga vmebus controller vhdl testbench code Contextual Info: Optimized for VME64 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME	Original	vme64 sept/2003 vhdl code for door rtsx72 +6vhdl synchronous parallel bus apa600 interrupt controller verilog code interrupt controller verilog 656 fpga vmebus controller vhdl testbench code	PDF
automotive canbus Abstract: 128x11 Contextual Info: iniCAN Controller Area Network Interface and Inicore, a CoreHDL Partner Features • • • • • • • • General Description CANbus 2.0B, originally developed for the European car industry, is a fast, secure, and cost-effective data bus for multi-master and realtime applications. In addition to automotive applications, it is suitable	Original	5172126-1f automotive canbus 128x11	PDF
Contextual Info: iniG704-E1 Universal ISDN E1 Framer and Inicore, a CoreHDL Partner Features • • • • • • • • • • • • General Description The iniG704-E1 framer core is designed to structure data flows in ISDN systems for the telecommunications market. It’s a universal	Original	inig704-e1 5172127-0f	PDF
vme vhdl Abstract: APA150 Contextual Info: Optimized for VME A32D32 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME	Original	a32d32 sept/2003 vme vhdl apa150	PDF
Contextual Info: iniSCI I2C Bus Controller Interface and Inicore, a CoreHDL Partner Features • I2C-Compatible • Single Master • Programmable Baud Rate Generator 390–100 kbps with 1µs Clock Enable • Automatically Incremented Address Pointer • 3-Point Input Sampling, Glitch Rejection	Original	3200dx 1200xl 5172128-0f	PDF
VERILOG Digitally Controlled Oscillator Abstract: vhdl code for DCO verilog code for uart apb vhdl code for 4 bit even parity generator uart verilog code vhdl code for 8 bit ODD parity generator uart vhdl code fpga Contextual Info: D a ta s h e e t UART MODULE Revision 2.8.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com C O P Y R IG H T 2 0 0 1 - 2 0 0 4 , IN IC O R E , IN C . U A R T m o d u le D a ta s h e e t	Original	verilog digitally controlled oscillator vhdl code for dco verilog code for uart apb vhdl code for 4 bit even parity generator +3uart verilog code vhdl code for 8 bit odd parity generator uart vhdl code fpga	PDF
programming logic controller Abstract: 14 pin gpio port GPIO verilog code for apb Inicore Contextual Info: Datasheet GPIO MODULE Version 1.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2003 INICORE INC. GPIOmodule Datasheet Table of Contents 1	Original	programming logic controller 14 pin gpio port gpio verilog code for apb +1inicore	PDF
Contextual Info: Datasheet CANmodule-IIx Version 2.6.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com 2002-2004, INICORE, INC. CANmodule-IIx Datasheet Table Of Contents 1	Original		PDF
AT91R40807 Abstract: P1386 Silicon Sculptor II sdb 750 pc100 system board sram 16 mbyte Contextual Info: System-on-Chip from Spec to Silicon System Design Board SDB-750/1000 Features Product Description Inicore's System Design Board SDB-1000 provides a versatile platform for your next development. An ARM based CPU subsystem with 2 MBytes of SRAM and 16 MBytes of program	Original	sdb-750/1000 sdb-1000 198k-bits rs-232 +7com/sdb-750/1000 at91r40807 p1386 silicon sculptor ii sdb 750 pc100 system board sram 16 mbyte	PDF
EG125 Contextual Info: iniUART and Inicore, a CoreHDL Partner Universal Asynchronous Receiver/Transmitter Features • Configurable Transfer Rate: 1200 bps to 64 kbps with Accuracy Better than 0.1% from 8 MHz Clock • Data Format: 7 or 8 Bits • Parity Enable, Odd/Even, Parity Error Detection	Original	3200dx 1200xl rs-232 5172124-1f +1eg125	PDF
ISO-118980-1 Contextual Info: Datasheet iniCAN C ONTROLLER A REA N ETWORK PROTOCOL CONTROLLER Revision 2.0 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2001-2010 INICORE INC. iniCAN Datasheet	Original	iso-118980-1	PDF

verilog code for slave SPI with FPGA Abstract: vhdl code for spi vhdl spi interface VHDL code for slave SPI with FPGA SPI Timing Diagram Contextual Info: Datasheet SPIM MODULE Revision 2.2 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2002-2003, INICORE INC. SPIMmodule Datasheet Table of Contents 1	Original	verilog code for slave spi with fpga vhdl code for spi vhdl spi interface vhdl code for slave spi with fpga +1spi timing diagram	PDF
vme bus specification Abstract: VMEL VME64 VME64S D64-MBLT VME64-M vme core VME/ST6398 Contextual Info: Datasheet VME64M VME64 M ASTER C ONTROLLER Version 1.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2007-2008, INICORE INC. VME64M Datasheet Ta b l e o f C o n t e n t s	Original	vme64m vme64 vme bus specification vmel +5vme64s d64-mblt vme64-m vme core vme/st6398	PDF
vhdl code for Clock divider for FPGA Abstract: AMBA BUS vhdl code Contextual Info: Datasheet TIMER MODULE Version 1.2.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com COPYRIGHT 2003 INICORE INC. TIMERmodule Datasheet Table of Contents 1	Original	vhdl code for clock divider for fpga amba bus vhdl code	PDF
ISO 11898-1 Abstract: round robin bus arbitration ROUND ROBIN ARBITRATION AND FIXED PRIORITY SCHEME CANopen Contextual Info: Datasheet CANmodule-III Version 2.2.1 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 t: 510 445 1529 f: 510 656 0995 e: info@inicore.com www.inicore.com 2002-2004, INICORE, INC. CANmodule-III Datasheet Table Of Contents 1	Original	iso 11898-1 round robin bus arbitration round robin arbitration and fixed priority scheme canopen	PDF
baudrate Abstract: UART DESIGN Contextual Info: iniUART data sheet Features: • Configurable Transfer Rate: 1200bps to 115.2kbps with Accuracy Better than 0.1% from 8MHz Clock! • Data Format: 7, 8 Bits • Parity Enable, Odd/Even, Error Detection • Stop Bit: 1, 2 Bits • Format Check • 3-Point Input Sampling, Glitch Rejection	Original	1200bps 391-ds-14 baudrate uart design	PDF
phase detector in RTL Abstract: ADPLL phase detector CH-2555 ADPLL with low jitter Contextual Info: iniADPLL All Digital Phase Locked Loop Features • • • • • • • • • General Description The iniADPLL is an all digital implementation of a phase locked loop. PLLs are widely used in telecom applications for clock recovery, clock generation and clock supervision. The all digital solution needs no external	Original	phase detector in rtl adpll phase detector ch-2555 +1adpll with low jitter	PDF
BOSCH CAN Abstract: DLC3 BOSCH CAN vhdl id28 PCA82C250T ID-28 DLC2 Contextual Info: iAP-CANaccess APB t lian p m o c data sheet A AMB Features: • CAN 2.0B, up to 1Mbit/s • Trace Capability on Bit Level • AMBA (APB) compliant interface • Access to all Internal Status, Error Counters • Frame Reference, TX Bus, RX Bus internally and externally available (FIFO	Original	pca82c250t bosch can dlc3 bosch can vhdl +3id28 id-28 dlc2	PDF
BOSCH fpg Abstract: A32140DX PCA82C250T PQFP160 Bosch TMS Contextual Info: CANaccess A FPG n o B . CAN2 data sheet Features: • CAN 2.0B, up to 1Mbit/s • Trace Capability on Bit Level • MC683xx compatible Interface 300 ns • Access to all Internal Status, Error Counters • Frame Reference, TX Bus, RX Bus internally and externally available (FIFO	Original	mc683xx a32140dx pqfp160 312-ds-12 +3bosch fpg pca82c250t bosch tms	PDF
bosch motronic Abstract: motronic bosch torque sensor bosch j1939 Bosch Washing machine CPU STARTER CUTLER HAMMER bosch washing machine motor bosch wheel speed sensor bosch injection cpu bosch motronic 1.3 Contextual Info: CONfROL ENGINEERING An Inside Look at the Fundamentals of CAN HOLGER ZELTWANGER. CAN in Automation Users and Manufacturers Group e.V. Erlangen. Germany intelligent I/O devices as well as sensors and actuators within a machine or plant. The textile machinery industry is one	OCR Scan	bosch motronic motronic bosch torque sensor bosch j1939 +6bosch washing machine cpu starter cutler hammer bosch washing machine motor bosch wheel speed sensor bosch injection cpu bosch motronic 1.3	PDF
ISO 11898-1 Abstract: Controller Area Network Contextual Info: PSoC Creator Component Datasheet Controller Area Network CAN 2.30 Features • CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant •     Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK) Two-wire or three-wire interface to external transceiver (Tx, Rx, and	Original	iso-11898-1 iso 11898-1 controller area network	PDF

INICORE Search Results

INICORE Datasheets (7)

INICORE Datasheets Context Search

alarm clock verilog code

RTSX72S

vhdl code for door

automotive canbus

vme vhdl

VERILOG Digitally Controlled Oscillator

programming logic controller

AT91R40807

EG125

ISO-118980-1

verilog code for slave SPI with FPGA

vme bus specification

vhdl code for Clock divider for FPGA

ISO 11898-1

baudrate

phase detector in RTL

BOSCH CAN

BOSCH fpg

bosch motronic

ISO 11898-1