IMSA Search Results

Contextual Info: 5.08mm .200" Pitch Wafer 5 \\E 182481 Features: • Avolofcle in 0 2 through 12 Ofoufai • U ateriot Nyton 6 6 UL94V-2 • Nota with 43 3 2 -HW Serin Hoisirg • 1.14nm(iMSa) Squad Ph • Pin Material: Bross/Tn-Rcted Specifications: B ±0.25 P itc h betw een poise

IMSA100G21S

Abstract: IMSA100 cascade shift register IMSA100-G21S digital correlator IMS100 A100G a100 dsp IMSA100-G211 IMS-A100
Contextual Info: S G S -T H O M S O N IMSA100 im ra s M iK s s CASCADABLE SIGNAL PROCESSOR • FULL 16 BIT, 32 STAGE, TRANSVERSAL FIL­ TER ■ FULLY CASCAD ABLE WITH NO SPEED DE­ GRADATION OR REDUCTION IN DYNAMIC RANGE ■ CO EFFICIENTS SELECTABLE AS 4, 8, 12, OR 16 BITS W IDE

inmos a110

Abstract: AN548 A110 IMSA110
Contextual Info: APPLICATION NOTE THE IMSA110 BACK-END POST PROCESSOR SUMMARY Page 1. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. 2.1 2.2 2.3 2.3.1 2.3.2 2.4 2.4.1 2.4.2 DESCRIPTION OF THE BACKEND POST PROCESSOR . . . . . . . . . . . . . . . . . . . . . .

SYNCMOS

Abstract: IMSAP-D003
Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D003 44L PQFP Package Outline： B e 0.25 θ Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A ─ ─ 2.70 ─ ─ 0.106 A1 0.05 ─ 0.50 0.002 ─ 0.020 A2 1.90 ─ 2.20 0.075 ─ 0.087 B 0.29

Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D008 64L LQFP Package Outline： Symbol A A1 A2 b c D D1 E E1 e L L1 y θ Dimension in mm Dimension in inch Min Nom Max Min Nom Max ─ 0.05 1.35 0.17 0.09 11.90 9.90 11.90 9.90 ─ 0.45 ─ ─ ─ ─ ─ ─

IMSA110S

Abstract: A110 IMSA110
Contextual Info: APPLICATION NOTE THINNING DIGITAL PATTERNS USING THE IMSA110 SUMMARY Page 1. 1.1 1.2 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THINNING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

imsa

Abstract: A110 IMSA110 542-l
Contextual Info: APPLICATION NOTE CASCADING IMSA110s 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. 2.1 2.2 OPERATION OF A SINGLE IMSA110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IMSA110

Abstract: IMSA110-G20S PGA100
Contextual Info: IMSA110 IMAGE AND SIGNAL PROCESSING SUB–SYSTEM 1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS 0 — 1120 STAGES 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE 21 MULTIPLY-AND-ACCUMULATE STAGES 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW

DIGITAL COLOR TV RECEIVER

Abstract: TDA8118D dual channel digital volume control SDA5343 M3004LAB1 tv transmitter amplifier circuit remote control circuit for audio amplifier TDA8215A deflection amplifier horizontal infrared remote control switch
Contextual Info: ALPHANUMERICAL INDEX Type Number Function Page Number AVS08 Automatic Voltage Switch AVS10 Automatic Voltage Switch 49 AVS12 Automatic Voltage Switch 55 43 IMSA113 Image Coding Device 61 L272/M Dual Power Operational Amplifier 73 L272D Dual Power Operational Amplifier

A110

Abstract: IMSA110
Contextual Info: APPLICATION NOTE THINNING DIGITAL PATTERNS USING THE IMSA110 SUMMARY Page 1. 1.1 1.2 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THINNING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IMSA110-G20S

Abstract: IMSA110S IMSA110 PGA100 A11004
Contextual Info: IMSA110 IMAGE AND SIGNAL PROCESSING SUB–SYSTEM 1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS 0 — 1120 STAGES 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE 21 MULTIPLY-AND-ACCUMULATE STAGES 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW

PQFP144

Abstract: decoder PQFP160 IMSA110 PGA100 PQFP100 mpeg PQFP-144 video decoder STI3500
Contextual Info: PROCESSORS & PERIPHERALS DIGITAL COMPRESSION Type IMSA110 STi3220 STi3520 STi3520A STi3430 STi3400 STi3500A STi3520M STi4500 STi4510 Description Image and Signal Processor Motion Estimation Processor MPEG Audio/MPEG-2 Video Integrated Decoder MPEG Audio/MPEG-2 Video Decoder with Memory Optimization

SYNCMOS

Abstract: D006 002-L
Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D006 48L LQFP Package Outline： Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A ─ ─ 1.60 ─ ─ 0.063 A1 0.05 ─ 0.15 0.002 ─ 0.006 A2 1.35 ─ 4.15 0.053 ─ 0.163 B 0.17 ─ 0.27

64L TQFP

Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D007 64L TQFP Package Outline： θ Symbol A A1 A2 b c D D1 E E1 e L L1 y θ Dimension in mm Dimension in inch Min Nom Max Min Nom Max ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ 1.20 0.15 1.05 0.27 0.20 12.10 10.10

20LSOP

Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D005 20L SOP Package Outline： Symbol Dimension in mm Min Nom Dimension in inch Max Min Nom Max A ─ ─ 2.64 ─ ─ 0.104 A1 0.10 ─ 0.30 0.004 ─ ─ A2 2.18 ─ 2.39 0.086 ─ 0.094 B ─ 0.40 ─ ─

Contextual Info: APPLICATION NOTE THE IMSA110 BACK-END POST PROCESSOR SUMMARY Page 1. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. 2.1 2.2 2.3 2.3.1 2.3.2 2.4 2.4.1 2.4.2 DESCRIPTION OF THE BACKEND POST PROCESSOR . . . . . . . . . . . . . . . . . . . . . .

sonar beamforming

Abstract: IMSA113 IMS A121
Contextual Info: SCS-1ItLIOT * H0MS0N IMSA113 PROGRAMMABLE LENGTH DIGITAL DELAY LINE PRELIMINARY DATA • VARIABLE LENGTH 5-1317 CYCLES LATENCIES OF 6-1318 ■ FULLY CASCADABLE IN WIDTH AND LENGTH ■ AUTO-ZEROING OF DATA ON LENGTH CHANGE ■ UP TO 20MHz DATA RATE ■ FULLY STATIC HIGH SPEED CMOS IMPLE­

A110

Abstract: IMSA110 SGS-Thomson dn IMSA110S
Contextual Info: APPLICATION NOTE CASCADING IMSA110s 1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. 2.1 2.2 OPERATION OF A SINGLE IMSA110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

scr tic 1060

Contextual Info: ¿ = 7 S G S -T H O M S O N IMSA110 IMAGE AND SIGNAL PROCESSING SUB-SYSTEM • 1-D/2-D SOFTWARE CONFIGURABLE CON­ VOLVER/FILTER ■ ON-CHIP PROGRAMMABLE LINE DELAYS 0 — 1120 STAGES ■ 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE ■ 21 MULTIPLY-AND-ACCUMULATE STAGES

psri

Abstract: a110 IMSA110 IMSA110-G20S PGA100 A11007
Contextual Info: IMSA110 IMAGE AND SIGNAL PROCESSING SUB–SYSTEM 1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS 0 — 1120 STAGES 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE 21 MULTIPLY-AND-ACCUMULATE STAGES 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW

Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D002 44L PLCC Package Outline： Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A 4.19 ─ 4.70 0.165 ─ 0.185 A1 0.51 ─ 0.65 0.020 ─ 0.026 A2 3.68 ─ 4.01 0.145 ─ 0.158 B 0.33 ─ 0.56

SYNCMOS

Contextual Info: SyncMOS Technologies International, Inc. IMSAP-D001 40L PDIP 600mil Package Outline： Symbol Dimension in mm Dimension in inch Min Nom Max Min Nom Max A ─ ─ 5.59 ─ ─ 0.220 A1 0.25 ─ ─ 0.010 ─ ─ A2 3.18 ─ 4.95 0.125 ─ 0.195 B 0.36 ─

IMSA100

Abstract: IMS100 SA100G
Contextual Info: / = T S G S -m O M S O N IMSA100 CASCADABLE SIGNAL PROCESSOR • FULL 16 BIT, 32 STAGE, TRANSVERSAL FIL­ TER ■ FULLY C ASC ADABLE WITH NO SPEED DE­ GRADATION OR REDUCTION IN DYNAMIC RANGE ■ CO EFFICIENTS SELECTABLE AS 4, 8, 12, OR 16 BITS W IDE ■ DATA THRO UG H PUT TO 15.0 MHZ

mbed LPC1768

Abstract: cortex my Data Logger ARM 7 LPC1768 UART REGISTERS NXP LPC1768 transformerless ethernet design cmsis lpc1768 Transformerless Ethernet App LPC1768 DaC code example LPC1768 ADC code example UART Program Examples CORTEX
Contextual Info: S ILICON UPDATE by Tom Cantrell Circuit Cellar, the Magazine for Computer Applications. Reprinted by permission. For subscription information, call 860 875-2199, or visit www.circuitcellar.com. Entire contents copyright 2009 Circuit Cellar Inc. All rights reserved.