IEEE11 Search Results

FCBGA* 19x19

Abstract: MDIO 19X19 TLK6B008 ieee1149.1 mdio termination
Contextual Info: TLK6B008 OCTAL 6.25/3.125/1.25 GBPS BACKPLANE TRANSCEIVER SLLS608 − JANUARY 2004 D Octal 6.25G/3.125G/1.25Gbps 2:1 MUX/1:2 D D D D D Supports IEEE1149.1 JTAG D Supports IEEE802.3 Defined MDIO Serial DEMUX Devices for Serial Backplane Applications 4-Tap Adaptive Receive Equalizer to

Contextual Info: Ultra37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD Features — tpD = 12 ns — ts = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6 .5 ns • Product-term clocking — 3.3V ISR • IEEE1149.1 JTAG boundary scan

O16I

Abstract: 7256P 99L0
Contextual Info: PREUM INAm Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD — tco = 4.5 ns Features Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

SCANPSC110F

Abstract: SCANPSC110FDMQB SCANPSC110FFMQB SCANPSC110FLMQB
Contextual Info: SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan

linked state machines

Abstract: X3215 XAPP007 XAPP007O XAPP007V XC3000 XC3020 8 shift register by using D flip-flop
Contextual Info: Boundary-Scan Emulator for XC3000  XAPP 007.001 Application Note By BERNIE NEW Summary CLBs are used to emulate IEEE1149.1 Boundary Scan. The LCA device is configured to test the board interconnect, and then reconfigured for operation. Specifications Tests Supported

SCANPSC110FFMQB

Abstract: PSC11 SCANPSC110F SCANPSC110FDMQB SCANPSC110FLMQB SCANPSC110FSC SCANPSC110FSCX
Contextual Info: + / March 1998 P A IF ?C H II_ D SEMICONDUCTOR i SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) General Description Features The SC ANPSC 110F Bridge extends th e IEEE Std. 1149.1 test bus into a m ultidrop test bus environm ent. The advan­

Contextual Info: Semiconductor SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SC AN PSC 110F Bridge extends th e IEEE Std. 1149.1 test bus into a m ultidrop te st bus environm ent. The advan­

O96-I

Contextual Info: fax id: 6149 1Ult ra372 56 V PRELIMINARY Ultra37256V UltraLogic 256-Macrocell 3.3V ISR™ CPLD • Up to 192 I/Os — plus 5 dedicated inputs including 4 clock inputs • Product-term clocking • IEEE1149.1 JTAG boundary scan • Programmable slew rate control on individual I/Os

FIRECRON

Abstract: AS91L1002 L100 LQFP-100 MO-192 10F100-I Flash Memory Product Selector Guide 10F100-C JTS02 10L100
Contextual Info: AS91L1002 July 2004 JTAG Test Sequencer Description The AS91L1002 device provides a solution to perform stand alone IEEE1149.1 tests with out any third party test hardware. The device executes tests that have been translated from the Serial Vector Format SVF to

code 4 bit LFSR

Abstract: h bridge CSP
Contextual Info: SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan

CY37256VP160-100AC

Abstract: h jtag
Contextual Info: fax id: 6149 PRELIMINARY Ultra37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 10 ns Features — tS = 5.5 ns • 256 macrocells in sixteen logic blocks • IEEE standard 3.3V operation — 3.3V ISR — tCO = 6.5 ns Product-term clocking IEEE1149.1 JTAG boundary scan

SCANPSC110

Abstract: SCANPSC110F SCANPSC110FDMQB SCANPSC110FFMQB SCANPSC110FLMQB lfsr16
Contextual Info: O ctober 1999 SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support The 6 slot inputs support up to 59 unique addresses, a Broadcast Address, and 4 M ulti-cast G roup Addresses General Description The SC AN PSC 110F Bridge extends the IEEE Std. 1149.1

Contextual Info: fax id: 6150 CYPRESS PRELIMINARY Ultra37192 UltraLogic 192-Macrocell ISR™ CPLD Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os Low power option on individual logic block basis 5V and 3.3V I/O capability

IEEE-1101.10

Contextual Info: Type 15H, 9U - 19” Rackmount, High Availability Chassis featureS: • ■ ■ ■ ■ ■ ■ ■ ■ ■ 19” Rackmount/ Desktop fully compliant to IEEE1101.10/.11 9U x 84HP x 290mm H x W x D 8, 16 or 21-slot, PICMG: 2.0, 2.16, 2.17, backplanes (H.110 optional)

Contextual Info: S E M IC O N D U C T O R tm SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SC AN PSC 110F Bridge extends th e IEEE Std. 1149.1 test bus into a m ultidrop test bus environm ent. The advan­

IRS 740

Abstract: linked state machines XAPP007 X3213A X321 XC3000 XC3020A XC4000 X3208A
Contextual Info: APPLICATION NOTE Boundary-Scan Emulator for XC3000 Series  XAPP 007 March 11, 1997 Version 1.1 Application Note by Bernie New Summary CLBs are used to emulate IEEE1149.1 Boundary Scan. The FPGA is configured to test the board interconnect, and then reconfigured for operation.

Contextual Info: SCANPSC110F SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support Literature Number: SNOS136C SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) General Description

Contextual Info: fax id: 6148 CYPRESS PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features — ts = 4.5 ns — tco = 5.0 ns • 256 macrocells in sixteen logic blocks • In-System Reprogram mable ISR™ Product-term clocking IEEE1149.1 JTAG boundary scan

lem la 100-P

Abstract: E1101
Contextual Info: Ultra37128 P R E U M IN A m UltraLogic 128-Macrocell ISR™ CPLD Features — t co = 4.5 ns P ro d uct-term clo ckin g • 128 m a cro c ells in eig h t logic blocks IEEE1149.1 JTAG b o u n d a ry scan • In-S ystem R e p ro g ra m m ab le IS R ™

CY37256P160-125AI

Abstract: 37256P160 ieee1149.1 cypress 37-25615
Contextual Info: fax id: 6148 1Ult ra372 56 PRELIMINARY Ultra37256 UltraLogic 256-Macrocell ISR™ CPLD Features • • • • • • • • • Product-term clocking IEEE1149.1 JTAG boundary scan Programmable slew rate control on individual I/Os Low power option on individual logic block basis

Contextual Info: SCANPSC110F SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support OBSOLETE PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right

M28B

Abstract: MS-013 SCANPSC110F SCANPSC110FSC
Contextual Info: Revised August 2000 SCANPSC110F SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port IEEE1149.1 System Test Support General Description Features The SCANPSC110F Bridge extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a hierarchical approach over a single serial scan

Contextual Info: PREUM INAm Ultra37512 UltraLogic 512-Macrocell ISR™ CPLD — t co = 6 n s Features P ro d uct-term clo ckin g • 512 m a cro c ells in 32 logic blocks IEEE1149.1 JTAG b o u n d a ry scan • In-S ystem R e p ro g ra m m ab le ™ IS R ™ P ro g ram m a b le slew rate co n tro l on ind ividu al l/O s

SCAN90CP02

Abstract: IEEE-1149 bsdl
Contextual Info: Fault Insertion using IEEE1149.1 Silicon implementation and tool support. Ken Filliter: National Semiconductor Ken.Filliter@nsc.com Pete Collins: JTAG Technologies petec@jtag.co.uk High availability systems often include fail-over mechanisms that continually monitor