IEEE 32 BIT FLOATING POINT MULTIPLIER Search Results

DSP-3201

Contextual Info: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point

Contextual Info: AN ALO G D E V IC E S □ IEEE Floating-Point DSP Microprocessor FEATU RES 20 MHz IEEE Floating-Point Processor IEEE 32-Bit Single-Precision and 40-Bit Extended Single-Precision Floating-Point Formats 32-Bit Fixed-Point Formats, Integer and Fractional Separate Program and Data Buses Extended Off-Chip

ADSP-3201

Abstract: ADSP3201
Contextual Info: ANALOG DEVICES □ 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEA T U R ES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point

ADSP-3201

Abstract: ADSP-3221 ADSP-1401 adsp3201 ADSP3202 ADSP-3202 ADSP-3128 ADSP3210 HB FULLER ADSP-3210
Contextual Info: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Com plete Chipset Im plementing Floating-Point Arithm etic Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point

268-5400

Abstract: weitek 268-5400-00 WTL1032 1u040 WTL1033 J1439
Contextual Info: A- B, W OODARD & AS SO C INNOVATIONS IN MICROSYSTEM TECHNOLOGY WTL1032 WTL1033 4 0 8 7 3 3 -7 3 5 3 High-Speed 32-Bit IEEE Floating Point Multiplier High-Speed 32-Bit IEEE Floating Point ALU Features A complete floating-point arithmetic solution for high-speed processors

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier _ ADSP-3210 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier.

ADSP-3210

Abstract: ADSP3210 b 806
Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier _ ADSP-3210 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier.

Contextual Info: L64133 32-Bit HCMOS IEEE Floating-Point Processor Description LSI LOGIC The L64133 is a high-speed processor which contains a full 32-bit floating-point multiplier and a full 32-bit floating-point ALU on a single chip. This three-bus device has a clean archi­

F2KV

Contextual Info: L64133 32-Bit HCMOS IEEE Floating-Point Processor LSI LOGIC Preliminary Description The L64133 is a high-speed processor which con­ tains a full 32-bit floating-point multiplier and a full 32-bit floating-point ALU on a single chip. This three-bus device has a clean architecture with no

weitek

Abstract: ncl051 WTL1165-060-GC 80386 microprocessor pin out diagram floating point handling LT 5251 1N3062 68-PIN WTL1163 1164-060
Contextual Info: WTL 1164/WTL 1165 64-BIT IEEE FLOATING POINT MULTIPLIER/ DIVIDER AND ALU PRELIMINARY DATA Features A COMPLETE FLOATING POINT ARITHMETIC SOLUTION FOR HIGH-SPEED PROCESSORS AND COPROCESSORS FULL 32-BIT AND 64-BIT FLOATING POINT FORMAT AN D OPERATIONS, CONFORMING TO

c3200 BL

Abstract: TMC3200 nana j12 ir TMC3201 marking CYN C3200 equivalent TMC3200G5A
Contextual Info: TRYw TMC3200, TMC3201 CM O S Floating-Point Arithmetic Unit and Multiplier 32/34 Bits The TMC3200, an arithmetic unit, adds and subtracts floating-point numbers expressed in IEEE 32-bit single­ precision format or extended-range 34-bit format. Conversions between floating-point and 24-bit two'scomplement integer fixed-point representations are

3222S

Contextual Info: ANALOG DEVICES □ FEATURES Complete 40 MFLOPS Floating-Point Chipset Multiplier/Divider and ALU Fully Compatible w ith IEEE Standard 754 Arithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point 64-Bit Double-Precision Floating-Point

Contextual Info: SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file

Contextual Info: ANALOG DEVICES □ 64-Bit IEEE Floating-Point Chipset ADSP-3212/ADSP-3222 FEATURES Com plete 40 MFLOPS Floating-Point Chipset M ultiplier/D ivider and ALU Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point

F2KV

Abstract: 4x4 bit multipliers sulzer 8400 a11xx
Contextual Info: L64133 32-Bit HCMOS IEEE Floating-Point Processor Preliminary Description T ST LOGIC •T T . V . X T WW M U f f S S The L64133 is a high-speed processor which con­ tains a full 32-bit floating-point multiplier and a full 32-bit floating-point ALU on a single chip. This

ADSP-21160

Abstract: ADSP-21161 ADSP-21262 ADSP-21266 BLM18AG102SN1D 20BIT ADC
Contextual Info: SHARC Embedded Processor ADSP-21262 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

ADSP-21160

Abstract: ADSP-21161 ADSP21261 ADSP-21261
Contextual Info: SHARC Embedded Processor ADSP-21261 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

spi flash parallel port

Abstract: ADSP-21160 ADSP-21161 ADSP-21262 ADSP-21266 A2388
Contextual Info: SHARC Embedded Processor ADSP-21262 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

m15m R2

Abstract: ADSP-21XXX architecture ADSP-21020 adsp21020kg133
Contextual Info: ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution

Contextual Info: 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maxim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

Contextual Info: A. e PREHj INNOVATIONS IN MICROSYSTEM TECHNOLOGY WOODARD & ASSOC. ä\ T / ä 408 7 3 3 -7 3 5 3 WTL1032 High-Speed 32-Bit IEEE Floating Point Multiplier WTL1033 High-Speed 32-Bit IEEE Floating Point ALU Features A co m p lete flo atin g -p o in t a rith m etic solu tion

Contextual Info: WTL 2264/WTL 2265 FLOATING POINT MULTIPLIER/ DIVIDER AND ALU PRELIMINARY DATA April 1986 Features HIGH SPEED CONFORMANCE TO IEEE STANDARD 754, VERSION 10.0 Full 32-bit and 64-bit floating point formats and opera­ tions 20 MFlops 50 ns pipelined for 32-bit ALU opera­

DSP-21020

Abstract: DSP21020
Contextual Info: NOV 3 m ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

M 3211

Abstract: Rapa SP-3211 SP3211
Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier ADSP-3211 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: