IE1A Search Results

siemens sab 82538

Abstract: 3tb siemens T-0657 SiEMENS PM 350 98 SAB 80188 QD70 SIEMENS ESCC8 1fa MARKING processor hbt 00 04 g Q67100-H6441
Contextual Info: SIEM ENS Enhanced Serial Communication Controller ESCC8 SAB 82538 SAF 82538 Preliminary Data 1 CMOS 1C General Features Serial Interface • Eight independent full duplex serial channels - On chip clock generation or external clock source - On chip DPLL for clock recovery of each

LBIT 204

Abstract: TA 8515 F AT90S4414 DIAGRAM AVR GENERATOR analog pds AT90S8515a AT90S8515 at90s85158jc
Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR - High-performance and Low-power RISC Architecture - 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 8 MIPS Throughput at 8 MHz • Data and Nonvolatile Program Memory

015E

Abstract: AT90S4414 SP14 SP15 90S4414
Contextual Info: AT90S4414 Features • Utilizes the AVR Enhanced RISC Architecture • A V /7- High Performance and Low Power RISC Architecture • 120 Powerful Instructions - Most Single Clock Cycle Execution • 4K bytes of In-System Reprogrammable Downloadable Flash

AT908515

Abstract: AT90S8515P AT90S8515JC AT90S8515PC AT90S8515 SP14 SP15
Contextual Info: AT90S8515 Features • Utilizes the M R Enhanced RISC Architecture • A V /7- High Performance and Low Power RISC Architecture • 120 Powerful Instructions - Most Single Clock Cycle Execution • 8K bytes of In-System Reprogrammable Downloadable Flash

D403a

Abstract: Z16C3010gmb burn-in SS00010 44s3 AETA
Contextual Info: PRELIMINARY MILITARY PRODUCT SPECIFICATION Z16C30 C M O S USC U niversal S erial C ontroller ZILGS016 •l PRELIMINARY MILITARY PRODUCT SPECIFICA TION < £ > Z iiæ Z16C30 CMOS U SC U n iv e r s a l S e r ia l C o n t r o ll e r FEATURES • 32 byte data FIFO's for each receiver and transmitter.

Contextual Info: ADVANCE MT4LC16256/7 S 256K X 16 DRAM IC R O N DRAM 256K x 16 DRAM 3.3V FAST PAGE MODE, OPTIONAL SELF REFRESH FEATURES • Industry-standard x l6 pinouts, tim ing, functions and packages • High-perform ance CM OS silicon-gate process • Single +3.3V ±0.3V pow er supply’

Contextual Info: SAB 82538 SAF 82538 SIEM ENS H D LC M ode D etailed R egister D escription In the register description the register addresses are specified by an “offset" relative to the “base addresses' , which are 000, 040, 080. 0C 0, 100, 140, 180, 1C0 for the eight

Contextual Info: AT90S4414 Features • • • • • • • • • • • • • • • • • • • • • Utilizes the AVR Enhanced RISC Architecture M R - High Performance and Low Power RISC Architecture 120 Powerful Instructions - Most Single Clock Cycle Execution

Contextual Info: Features • AV/7 - High Performance and Low Power RISC Architecture • 118 Powerful Instructions - Most Single Clock Cycle Execution • 4K bytes of In-System Reprogrammable Flash - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles

Contextual Info: Features AVR - High Performance and Low Power RISC Architecture 118 Powerful Instructions - Most Single Clock Cycle Execution 8K bytes of In-System Reprogrammable Flash - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles 512 bytes EEPROM

Contextual Info: Features • Utilizes the AVR RISC Architecture • AVR - High-performance and Low-power RISC Architecture - 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 10 MIPS Throughput at 10 MHz • Data and Nonvolatile Program Memory

IC 200 UDR 005

Abstract: AT90S2313
Contextual Info: Features • AVR - High Performance and Low Power RISC Architecture • 118 Powerful Instructions - Most Single Clock Cycle Execution • 2K bytes of In-System Reprogrammable Flash - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles

ESCC8

Abstract: csc 2323 siemens sab 82538 random pattern generator tda 2652 MARKING 09F MARKING 1AB CRC-16 CRC-32 SAF 82538 H-10 ESCC8
Contextual Info: ICs for Communications Enhanced Serial Communication Controller with 8 Channels ESCC8 SAB 82538 SAF 82538 Version 2.2 User’s Manual 03.95 Edition 03.95 This edition was realized using the software system FrameMaker‚. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,

atm 8515

Abstract: at90s85158ac
Contextual Info: Features Utilizes the AVR RISC Architecture AVR - High-performance and Low-power RISC Architecture - 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 8 MIPS Throughput at 8 MHz Data and Nonvolatile Program Memory

KC156A

Abstract: ky202e K174XA2 KT809A KT805A KT610B KP350A KT808a KT920A KC213
Contextual Info: BJOJIABPHHEHKO CnPABOMHMK n o n o jiy nPOBOAHMKOBBIM nPMBOPAM H 3A aH ne 1 0 -e, nepepaöoT aH H oe KHEB «TEXHIKA* h flo n o jiH e H H o e 32.852 h2 J113 JlaBpnMenKO B. 10. J113 CnpaBOMHHK no noJiynpoBOAHHKOBbiM npnöopaM. 10-e m a., nepepaô. h A on.— K.: TexHiKa, 1984.— 424 c., hji.— BHÓjniorp.:

Contextual Info: Features • AVR - High-performance and Low-power RISC Architecture - 118 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Up to 8 MIPS Throughput at 8 MHz • Data and Nonvolatile Program Memories - 4K/8K Bytes of In-System Programmable Flash