IC TTL 74LS Search Results

2SA705

Abstract: 2SC632A LM301 EQUIVALENT transistor+2SA705 2SC632A equivalent
Contextual Info: CXA1096P SONY« 8-bit 20 MSPS Flash A/D Converter TTL I/O Evaluation Board Available — CXA1096PPCB Description CXA1096P is an 8-bit 20 MSPS high speed A/D converter IC. This IC is suitable for a wide range of applications where A/D high speed operation is required.

DN74LS364

Abstract: DN74LS364S
Contextual Info: PANASONIC 69 3 2 8 f 2 INDL/ELEK PANAS ON IC -CICÏ 7E » Ë J bTBEflSE 0[][]7a30 □ IN OL * E L E C T R O N IC 72C 07230 LS TTL DN74LSS/U-X . DN74LS364/DN74LS364S “ ö ~ 7 - C b5~ DN 74LS364/ DN74LS364S Octal Positive Edge-Triggerd D-Type Flip-Flops with 3 - s ta te Outputs

Contextual Info: October 1987 Revised January 1999 S E M IC O N D U C T O R !!^ 7-Stage CD4024BC 7-Stage Ripple Carry Binary Counter Features • Wide supply voltage range: ■ High noise immunity: 0.45 3.0V to 15V V qq ■ Low power TTL compatibility: or 1 driving 74LS typ.

7406n

Abstract: 7408n 74193N 7416N 7407N 74181N 74LS01N 7438N 7437N 74h00n
Contextual Info: CYFROWE UKtADY SCALONE TTL SERII UCY 74 . /UCA 64 . Wykaz oznaczen parametrów technicznych poj'emnosc Unii statyczny wspólczynnik wzmocnienia pr^dowego w ukladzie OE "21B pr^d bazy IB IC pr^d kolektora Icc pr^d zasilania ICC+ ICC" OD 011 ICCH ICCH-*'

74LS60

Contextual Info: LS TTL DN74LS Series DN74LS260 DN74LS260 Dual 5 -input P o sitiv e NOR Gates • Description D N 74LS60 c o n ta in s P-1 tw o 5 -in p u t p o sitiv e-lo g ic NOR g ate c irc u its. ■ Features • L o w p o w e r c o n s u m p tio n P d = 2 0 m W ty p ic a l

Contextual Info: R C H II- P S E M IC O N D U C T O R tm DM74AS240, 244 3-STATE Bus Driver/Receiver Features • Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Improved switching performance with less power dissipation compared with Schottky counterpart ■ Functional and pin compatible with 74LS and Schottky

Contextual Info: TOSHIBA TC74HCT240,244AP/AF/AFW T O S H IB A C M O S D IG IT A L IN T E G R A T E D C IR C U IT S IL IC O N M O N O L IT H IC TC74HCT240AP, TC74HCT240AF# TC74HCT240AFW TC74HCT244AP, TC74HCT244AF, TC74HCT244AFW OCTAL BUS BUFFER WITH TTL INPUT LEVEL TC74HCT240AP/ A F /A FW INVERTED, 3 - STATE OUTPUTS

54HC

Abstract: 74LS TTL 74LS MM54HC4302 MM74HC4302 74HC logic family
Contextual Info: National Semiconductor MM54HC4302/MM74HC4302 TTL Input Octal TRI-STATE Latch General Description This high s p e e d OCTAL D-TYPE LATCH is m anu facture d w ith silico n g a te C M O S te ch n o lo g y. All inp u ts a re c o m p a ti­ b le w ith TTL lo g ic le ve ls, re cog n izin g a ze ro input belo w

L 298

Abstract: 74LS298 panasonic tsu
Contextual Info: PANASONIC INDL/ELEK -CIO 72 6932,85 2 PANAS ONIC DeTÌ f ì 3 2 ù 5 2 3 W ' □□07553 IN DL«ELEC TR O N IC 72C LS TTL D N 7 4 L S ^ U —X 0 7223 D; T - 6 6 - 2 1 - 5 1 DN74LS298/DN74LS298S DN 74LS298/ DN 74LS298S Quad 2 -input M ultiplexers with Storage

XIFG

Contextual Info: P ANASONIC INDL/ELEK ÌICJ 72 69328.52 PANASONIC DE | >,*132055 □ □ □ 7 2 1 cì 1 IN D L *E L E C T R O N IC 72 LS TTL DN 74LS^'J-X C ' 0 7 2 1 9 . O 7 t/ 6 ' 0 9 ~0 J DN74LS295B/DN74LS295BS DN74LS295B/DN74LS295BS 4“ bit Bidirectional Universal Shift R egister

Ic 74hc138 logic diagram

Contextual Info: Revised February 1999 S E M IC Q N D U C T O R T M MM74HC138 3-to-8 Line Decoder The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to V qq and ground.

Contextual Info: SGS-THOMSON M54HCT157/158 ^ 7# « IR m iC T « !_ M74HCT157/158 HCT157 QUAD 2 CHANNEL MULTIPLEXER HCT158 QUAD 2 CHANNEL MULTIPLEXER INV. • HIGHSPEED tPD = 21 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 4 nA (MAX.) AT Ta = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS

inductosyn

Abstract: 2s80 5s72 CMOS 4063 STM1680 DRC1765 3S16 inductosyn farrand resolver 90 scott-t transformer
Contextual Info: A N A LO G D E V IC E S 14- & 16-Bit, Hybrid Digital-to-Resolver Converters AD2S65/AD2S66 FEATURES Single Rank Transparent TTL or CMOS Compatible Latched Input Registers W ith High and Low Byte ENABLE Accuracy ± 1 , ± 2 or ± 4 Arc Minutes Resolution 14- or 16-Bit

d92 02

Abstract: ttl 7497 D187 D188 D190 D194 D195 D196 74LS377 74ls175 pin diagram
Contextual Info: FAIRCHILD L O G IC /C O N N E C T IO N DIAGRAM S D IG ITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 11 — 0 CE 9 - CP 10— 0 Ez 1 2 - Gy k h IE 7 TC 3 4 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8 D190 54LS/74LS375 Vcc = Pin 16

"Binary Multipliers"

Abstract: DN74LS261 pn74ls261
Contextual Info: PANASONIC INDL/ELEK -CIO 75 6932652 PA NASONIC 1>E | b^BSñSS D0Q711S 5 f 72C 07195 INDL. » E LECTRO N IC V Y S^^l D DN74LS261 /DN74LS261S LS TTL D N 7 4 L S ^ U -X DN74LS261/DN74LS261S 2-bit-B y-4-bit Parallel Binary Multipliers • m. m D N 74L S261/SIÍ,

Contextual Info: TDC1041 TDC1041 Monolithic Digital To Analog Converter 10 Bit, 20Msps, 12ns Settling Time The TDC1041 is a TTL co m p a tib le , 1 0 -b it m o n o lith ic D /A conve rter capable of conve rting d ig ita l data into an analog curre nt or volta g e a t data rates in excess o f 20 M egasam ples-per second M sps .

74HC02N

Abstract: 74HC02M
Contextual Info: A S E M I R C H I L D IC O N D U C T O Revised February 1999 R T M MM74HC02 Quad 2-Input NOR Gate General Description Features The MM 74H C 02 NOR gates utilize advanced silicon-gate C M OS tech n olo gy to achieve operating speeds sim ilar to LS-TTL gates w ith the low pow er consum ption of standard

shiftregisters

Abstract: EP910 altera TTL library 74LS series logic gates 74LS EP1810 EP1810-45 EP610 PLE40 altera logicaps TTL library
Contextual Info: EP1810 Y 7 \ m HIGH PERFORMANCE 4 8 MACROCELL EPLD m 10 I U FEATURES GENERAL DESCRIPTION • Erasable, User-Configurable LSI circuit capable of implementing 2100 equivalent gates of conven­ tional and custom logic. • Speed equivalent to 74LS TTL with 33 MHz clock

74LS589

Abstract: 74LS58 54LS58 SN74LS589
Contextual Info: TYPES SN54LS589, SN74LS589 8-BIT SHIFT REGISTERS WITH INPUT LATCHES AND 3-STATE OUTPUT REVISED DECEMBER 1983 ! • 8-B it Parallel S torage Register Inputs S N 54LS 589 . . . J PACKAGE SN 74LS589 . . . J OR N PACKAGE S h ift Register has D irect Overriding Load and

TTL 7414

Abstract: IC sn7414
Contextual Info: TYPES SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS _ REVISED DECEMBER 1983 SN 5414, SN 54LS14 . . . J OR W PACKAGE S N 7414 . . . J OR N PACKAGE SN 74LS 14 . . . D, J OR N PACKAGE | • Operation from Very Slow Edges

74ls593

Abstract: 8-bit binary counter 74LS593 74ls592
Contextual Info: TYPES SN54LS592, SN54LS593, SN74LS592, SN74LS593 8-BIT BINARY COUNTERS WITH INPUT REGISTERS 0 2 6 3 3 , J A N U A R Y 1981 - R E V IS E D D E C E M B E R 1 9 8 3 SN54LS592 . . . J OR W PACKAGE S N 74LS 592 . . . J OR N PACKAGE P araH ei '3egis \.s r In p u ts f'LSF'*'?

Contextual Info: SN54194, SN54LS194A, SN54S194, SN74194, SN74LS194A, SN74S194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS MARCH 1 9 7 4 —R EV ISED MARCH 1988 SN 54194, S N 54LS194A , S N 54S 194 . . . J OR W PACKAGE S N 7419 4 . . . N PACKAGE SN 74LS 19 4A , S N 7 4 S 1 9 4 . . . D OR N PACKAGE

counter 74490

Abstract: of 74ls90 IC decade counter
Contextual Info: TYPES SN54490, SN54LS490, SN74490, SN74LS490 DUAL 4-BIT DECADE COUNTERS O CTO BER Dual Versions of Popular SN 5490A, SN 54LS90, SN 7490A, and SN 74LS90 Counters 1 9 7 6 —R E V IS E D D ECEM BER 1983 SN 54490, SN 54LS490 . . . JO R W PACKAG E SN 74490 I OR N PACKAG E

SN54LS592

Abstract: SN74LS592 SN54LS593 SN74LS593 31145
Contextual Info: TYPES SN54LS592, SN54LS593, SN74LS592, SN74LS593 8-BIT BINARY COUNTERS WITH INPUT REGISTERS 0 2 6 3 3 , J A N U A R Y 1981 - R E v is E D DECEMBER 1983 S N 5 4 L S 5 9 2 . . . J OR W P AC K A G E SN 74LS592 I OR N P A C K A G E • Parallel Register Inputs "LS592