IBM CORECONNECT BUS Search Results

IBM processor

Abstract: PPC405 XILINX ipic 2VP7FF896-6 fpga frame buffer vhdl examples
Contextual Info: RapidIO Processor Buffer DS241 v1.0 December 20, 2002 Interface Specification Introduction LogiCORE Facts The RapidIO Processor Buffer provides an interface between the Xilinx Processor Local Bus—Intellectual Property Interface (PLB-IPIF) and the Xilinx 8-bit LP/LVDS

250 mhz IBM PowerPC Processor

Abstract: IBM PCI Express serdes architecture ibm ASIC SRAM SA-12E IBM ASIC Products ibm ip IBM supports ccga 0.25-um standard cell library IBM ASIC
Contextual Info: Standard cell/gate array ASIC for mainstream and cost-sensitive applications SA-12E ASIC Highlights Integration and performance deliver exceptional value. The IBM SA-12E ASIC is a standard  0.25-µm process technology cell and gate array ASIC, featuring a

SA-27E

Abstract: IBM PCI Express serdes architecture
Contextual Info: Standard cell/gate array ASIC for mainstream and cost-sensitive applications requiring fast time-to-market SA-27E ASIC Highlights Integration and performance deliver exceptional value. The IBM SA-27E ASIC is a dense,        • Gate delay: 33 picoseconds

ibm ASIC SRAM

Abstract: IBM "embedded dram" IBM supports ccga
Contextual Info: Standard cell/gate array ASIC for high-function, high-density applications Blue Logic Cu-11 ASIC Highlights 0.11-µm L drawn enables designs of up to 40 million gates Advanced technologies include copper metallurgy and low-k dielectric Choice of packaging options

SECDED

Abstract: PowerPC 401 powerpc 405gp uart code 128 bit register 440GP plb 405 440a4 "routing tables"
Contextual Info: PowerPC 440GP Embedded Processor: TM High performance SOC for networked applications IBM Microelectronics All information in these materials is subject to change without notice. All information is provided on an “as is” basis, without any warranty of any kind.

project of 8 bit microprocessor using vhdl

Abstract: XC4VSX35-10FF668C SDD44 UCF virtex4 XAPP729 vhdl code for sdram controller X729 DS426 ML470 MT48LC8M32B2
Contextual Info: Application Note: Virtex-4 FPGA Family R XAPP729 v1.0.1 March 4, 2007 Interfacing a 64-Bit DDR Memory Bus to a 32-Bit Microprocessor Bus Author: Marc Defossez Summary In today’s processor, digital signal processor (DSP), and other applications, memory data

XC5VLX220-FF1760

Abstract: xc5vlx220ff1760-2 DS442 XC4VLX200-FF1513-10 xc4vlx200ff1513
Contextual Info: OPB to DCR Bridge v1.00b DS442 April 24, 2009 Product Specification Introduction LogiCORE IP Facts The OPB to DCR Bridge translates transactions received on its OPB slave interface into DCR master operations. Its design utilizes an Intellectual Property

440GX

Abstract: DDR200 DDR200-DDR333 DDR333 dmips IBM powerpc 440gx IBM Processor Local Bus PLB 64-Bit Architecture
Contextual Info: PRODUC T BRIEF PowerPC 440GX Embedded Processor With speeds of up to 800 MHz, the PowerPC 440GX processor offers the versatility and bandwidth required for demanding networking and storage applications. This highly integrated device supports PCI-X bus devices and DDR333 memory. With embedded state-of-the-art peripheral cores, the 440GX processor is ideal

XAPP662

Abstract: PPC405 XAPP138 XAPP660 XAPP661 XC2VP20 FF1152 FF672 Virtex-II Platform FPGA Complete All Four Module verilog code of prbs pattern generator
Contextual Info: Application Note: Virtex-II Pro Family R XAPP662 v1.1 July 3, 2003 Summary In-Circuit Partial Reconfiguration of RocketIO Attributes Author: Vince Eck, Punit Kalra, Rick LeBlanc, and Jim McManus This application note describes in-circuit partial reconfiguration of RocketIO transceiver

PPC405

Abstract: XAPP655 XC2VP125 Virtex-II Platform FPGA Complete All Four Module "routing tables"
Contextual Info: Application Note: Virtex-II Pro Family R Mixed-Version IP Router MIR Author: Gordon Brebner XAPP655 (v1.0) November 19, 2002 Summary This application note describes a reference design for a mixed-version IP router (MIR) servicing up to four gigabit Ethernet ports. MIRs are useful where several gigabit Ethernet networks are

XAPP662

Abstract: FF672 PPC405 XAPP138 XAPP660 XAPP661 XC2VP20 XC2VP70 MG-17 x662
Contextual Info: Application Note: Virtex-II Pro Family R XAPP662 v2.4 May 26, 2004 Summary In-Circuit Partial Reconfiguration of RocketIO Attributes Author: Vince Eck, Punit Kalra, Rick LeBlanc, and Jim McManus This application note describes in-circuit partial reconfiguration of RocketIO transceiver

XAPP655

Abstract: Deframing PPC405 XC2VP100 RFC2766 "routing tables"
Contextual Info: Application Note: Virtex-II Pro Family R Mixed-Version IP Router MIR Author: Gordon Brebner XAPP655 (v1.2) October 13, 2004 Summary This application note describes a reference design for a mixed-version IP router (MIR) servicing up to four gigabit Ethernet ports. MIRs are useful where several gigabit Ethernet networks are

microblaze

Abstract: 32-bit microprocessor harvard architecture block diagram uart 16450 microblaze ethernet lite
Contextual Info: MicroBlaze RISC 32-Bit Soft Processor R August 21, 2002 Product Brief Features LogiCORE™ Facts • Supports Virtex, Virtex-E, Virtex-II Pro, Spartan-II, and Spartan-IIE devices • Performance: 102 Dhrystone MIPS D-MIPS on Virtex-II Pro device at 150 MHz

0x000000F9

Abstract: XAPP515 XAPP516 0xABCDEF12 0x300000FF
Contextual Info: Application Note: Embedded Processing R XAPP515 v1.0 May 19, 2006 Using Xilinx m4 Functions to Write Bus Functional Language Stimuli for CoreConnect Buses Author: Lester Sanders Summary This application note provides definitions and examples of Xilinx developed m4 functions used

PowerPC EBC 440spe

Abstract: DDR266 DDR333 DDR667 83 dhrystone
Contextual Info: PRODUCT BRIEF PowerPC 440SPe Embedded Processor Benefits • Delivers 533 MHz to 667 MHz performance for embedded I/O processor designs • 32-Kbyte–I/32-Kbyte- D L1 caches • 256-Kbyte L2 cache with parity protection, may also be used as on-chip SRAM • High-speed processor local bus

automatic rain wiper

Abstract: full automatic Washing machines microcontroller
Contextual Info: White Paper: MicroBlaze R WP167 v1.0 December 10, 2002 Field Programmable Controllers for Cost Sensitive Applications By: Richard Griffin Staying ahead of the competition is getting tougher everyday. Cost pressures, changing standards, and device obsolescence are just a few of the challenges.

Contextual Info: Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.0 June 13, 2002 Advance Product Specification Summary of Virtex-II Pro Features • • High-performance Platform FPGA solution including - Up to twenty-four Rocket I/O™ embedded multi-gigabit transceiver blocks (based on

Contextual Info: PowerPC 440GP Embedded Processor Data Sheet Features • PowerPC 440 processor core operating up to 500MHz with 32KB I- and D-caches • Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII. • On-chip 8 KB SRAM

DS404

Abstract: xbm 898
Contextual Info: OPB to PLB Bridge v1.00c DS404 April 24, 2009 Product Specification Introduction LogiCORE IP Facts The On-Chip Peripheral Bus (OPB) to Processor Local Bus (PLB) Bridge module translates OPB transactions into PLB transactions. It functions as a slave on the OPB side and a

Contextual Info: PowerPC 440GP Embedded Processor Data Sheet Features • PowerPC 440 processor core operating up to 400MHz with 32KB I- and D-caches • Selectable processor:bus clock ratios of 3:1, 4:1, 5:2, 7:2 • Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are

Contextual Info: PowerPC 440GP Embedded Processor Data Sheet Features • PowerPC 440 processor core operating up to 500MHz with 32KB I- and D-caches • Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII. • On-chip 8 KB SRAM

amcc 440

Abstract: Nand controller AMCC IBM powerPC schematics LynuxWorks 440GR PPC440 powerPC 440 schematics
Contextual Info: Product Brief PowerPC 440GR Evaluation Kit Enables comprehensive evaluation of the AMCC 440GR processor, while accelerating customers' hardware and software development time. Product Highlights • Comprehensive, easy-to-use evaluation kit designed for customer setup in 15

amcc ppc440

Abstract: AMCC PowerPC 440GX instruction set 440GX embedded powerpc 440GX IBM powerpc 440gx IBM powerPC schematics DDR333 PPC440 POWERPC440GX
Contextual Info: Product Brief PowerPC 440GX Evaluation Kit Enables comprehensive evaluation of the AMCC 440GX processor, while minimizing customers' hardware and software development time. Product Highlights • Comprehensive, easy-to-use evaluation kit designed for customer setup in 15

embedded powerpc 440

Abstract: uart 16750 09 N05 16750 UART PowerPC EBC 440GP IBM25PPC440GP-3CC400E IBM25PPC440GP-3CC400EZ IBM25PPC440GP-3CC466C IBM25PPC440GP-3CC466CZ
Contextual Info: PowerPC 440GP Embedded Processor Data Sheet Features • PowerPC 440 processor core operating up to 500MHz with 32KB I- and D-caches • Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII. • On-chip 8 KB SRAM