IBM CORECONNECT BUS Search Results

IBM CoreConnect bus

Contextual Info: IBM Microelectronics TM CoreConnect Bus Architecture A 32-, 64-, 128-bit core on-chip bus standard Highlights The IBM CoreConnect bus architecture eases the integration and reuse of processor, system, and peripheral cores within standard product and custom

AMBA AHB specification

Abstract: amba ahb bus arbitration master unit connected 4 slaves implementation PCI AHB bridge AMBA AHB bus arbiter
Contextual Info: Reducing cost and time to market for SoC designs IBM CoreConnect bus cores The embedded marketplace has a technology-based designs. IBM and The PLB on-chip bus is used in highly long history of system-on-a-chip SoC our ecosystem of I/O IBM Business integrated systems. It supports read

IBM39STB02100

Abstract: DSA0029232 IBM39 401B3 MUX21 real-time decoding IBM39STB I2C TRACE MUX23 ibm39stb02100pba22c
Contextual Info: IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers Features Overall • IBM Set-Top Box technology • Four major subsystems integrated with IBM onchip CoreConnect structure. • Maximum MIPS for OS and application tasks • Simplified driver and software development

PCI AHB DMA

Contextual Info: Reducing cost and time to market for SoC designs IBM CoreConnect and CPU support cores The embedded marketplace has a In addition, with each Power Design Kit, DMA to PLB4 controller long history of system-on-a-chip SoC IBM provides a bridge to the I/O core

chipscope manual

Abstract: ChipScope DS282
Contextual Info: Chipscope OPB IBA DS282 v2.5.1 Jan 16, 2004 Product Overview Introduction LogiCORE Facts The Chipscope OPB IBA core is a specialized Bus Analyzer core designed to debug embedded systems containing the IBM CoreConnect On-Chip Peripheral Bus (OPB). The

l2 cache design in verilog

Abstract: 476FP tag l2 ibm+powerpc+476fp powerpc 476FP
Contextual Info: A high-performance, on-chip system bus that supports coherency in multiple-core designs IBM CoreConnect PLB6 On-Chip System Bus Architectural features Highlights „ Support for concurrent traffic on read and write data buses „ Support for concurrent transfers on all segments

AMBA AHB bus arbiter

Abstract: ahb arbiter amba bus architecture rev 1.5 ibm amba ahb ahb bridge ahb2plb ARM946E-S ARM966E-S IBM Processor Local Bus PLB 64-Bit Architecture ibm rev 1.5
Contextual Info: Preliminary IBM AHB to PLB Bridge Core Overview Features The AHB to PLB Bridge is a soft core that permits transfers of code and data between the Advanced Microcontroller Bus Architecture AMBA Advanced High-performance Bus (AHB) and the CoreConnect Processor Local Bus (PLB).

IBM powerPC schematics 750

Abstract: IBM39STB
Contextual Info: IBM39STB032xx IBM39STB034xx Preliminary STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Features Overall • High-End Set-Top Box technology • Four major subsystems integrated with IBM on-chip CoreConnect structure. • Maximum MIPS for OS and application tasks

XILINX ipic

Abstract: DS414 DS413 IPIF SLV64 V301C fifo generator xilinx spartan chip select
Contextual Info: OPB IPIF v3.01c DS414 December 2, 2005 Product Specification Introduction LogiCORE Facts The OPB IPIF is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE™ products. It provides a bidirectional interface between a user IP core and

405B3

Abstract: RISCwatch 405 IBM39STB STB03xxx IBM39 powerpc
Contextual Info: IBM39STB032xx IBM39STB034xx Preliminary STB032xx and STB034xx Digital Set-Top Box Integrated Controllers Features Overall • High-End Set-Top Box technology • Four major subsystems integrated with IBM on-chip CoreConnect structure. • Maximum MIPS for OS and application tasks

0000001D

Contextual Info: Application Note DCR Addressing with the CoreConnectTM DCR Master Introduction This application note explains how to perform read and write operations on Device Control Registers DCR from a DCR Master to a Processor Local Bus (PLB) netlist core and a PLB Performance Monitor

amba bus architecture

Abstract: PPC440 AMBA AMBA APB bus protocol
Contextual Info: The CoreConnect Bus Architecture Recent advances in silicon densities now allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripherals formerly attached to the processor at the card level are integrated onto the same die as the processor. As a result, chip designers must now address issues

IBM processor

Abstract: PPC405 XILINX ipic 2VP7FF896-6 fpga frame buffer vhdl examples
Contextual Info: RapidIO Processor Buffer DS241 v1.0 December 20, 2002 Interface Specification Introduction LogiCORE Facts The RapidIO Processor Buffer provides an interface between the Xilinx Processor Local Bus—Intellectual Property Interface (PLB-IPIF) and the Xilinx 8-bit LP/LVDS

Contextual Info: Perspective PowerPC IBM’s New PowerPC Strategy Roadmap It’s exactly what you’d expect from IBM. Editor’s note: This article is reprinted with permission from IBM. It originally ran in the April, 2001, IBM PowerPC Processor News. You can view the original article at:

SA-27E

Abstract: IBM PCI Express serdes architecture
Contextual Info: Standard cell/gate array ASIC for mainstream and cost-sensitive applications requiring fast time-to-market SA-27E ASIC Highlights Integration and performance deliver exceptional value. The IBM SA-27E ASIC is a dense,        • Gate delay: 33 picoseconds

powerpc 405

Abstract: internet jukebox processor
Contextual Info: Inside Out Column - PowerPC and FPGAs Article Page 1 of 2 Home : Products : Publications : Inside Out : Article Inside Out Article Inside Out Home IBM PowerPC Solutions PowerPC architecture with Xilinx FPGAs – scaling new heights togethe Recently, a collaborative relationship was developed between IBM and Xilinx, combining the strengths

IBM powerpc 440gx

Abstract: embedded powerpc 440GX 440GX RISCwatch CU-11 DDR200 DDR200-DDR333 DDR333 powerpc 440gx 26Gbps
Contextual Info: A feature-rich processor optimized for high-speed networking and storage applications PowerPC 440GX Embedded Processor Highlights  Delivers 500 to 667MHz performance – with low power in a small form factor  Provides 256KB on-chip SRAM, configurable as an L2 cache or as

Marvell MV64460

Abstract: marvell discovery III MV64460 MV64560 MV64660 Marvell MV64560 mv64360 PowerPC 750gx DMIPS Marvell MV64360 TGB03005-USEN-00
Contextual Info: IBM Global Engineering Solutions IBM Power Architecture solutions IBM Power Architecture family • Information technology solutions The IBM Power Architecture such as blade servers, single- offerings — microprocessors family of processors ranges from

powerpc 405

Abstract: IBM powerpc 405
Contextual Info: Licensable processor cores for system-on-a-chip applications IBM PowerPC 405 Embedded Core Highlights • Compatible with the scalable and flexible IBM PowerPC instruction set architecture to facilitate ease of software migration ■ for emerging consumer, storage and

Contextual Info: News PowerPC Processors in Virtex-II FPGAs Partnerships IBM and Xilinx combine cutting edge technologies to create a revolutionary new product. by Ann Duft Manager of North American PR, Xilinx annd@xilinx.com IBM and Xilinx recently announced a partnership to create a new generation of devices

405EP

Abstract: 266MHZ SA-27E IBM405 Coreco IBM 202
Contextual Info: High-performance, low-power processor with two Ethernet MACs for embedded networking applications PowerPC 405EP Embedded Processor Highlights  Delivers up to 266MHz performance and a rich mix of features for Internet and communication products  Contains two Ethernet MACs to

powerpc 464

Abstract: 464-H90 PPC464FP PPC464FP-H90 CU-08 powerpc dhrystone PPC464-H90 IBM powerpc 464FP 464FP Cu-65
Contextual Info: High-performance design for custom logic applications PowerPC 464 and 464FP Embedded Processor Cores PowerPC processor core Highlights „ „ „ The PowerPC 464 and 464FP cores are dual-issue superscalar designs that provide high performance for custom logic applications.

Celoxica

Abstract: PCIX-66 XC2VP50
Contextual Info: New Product Virtex-II Pro Platform FPGA Virtex-II Pro FPGAs: The Platform for Programmable Systems Has Arrived The Virtex-II Pro solution heralds a paradigm shift in system architecture by moving design based on zones of programmability to entire system-level programmability.

BY128

Abstract: microcontroller using vhdl rtl series IBM Processor Local Bus PLB 64-Bit Architecture
Contextual Info: Application Note CoreConnect PLB Random-AutoMode Testcases Introduction This application note will explain the usage and operation of PLB Random-Automode Testcases. As a brief overview CoreConnectTM Toolkits contain a Bus Functional Compiler BFC that takes testcases