HD74AC1 Search Results

Contextual Info: HD74AC138/HD74ACT138 Description • 1 - o f- 8 Decoder/Demultiplexer Pin Assignment The HD74AC138/HD74ACT138 is a high-speed l-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow

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Contextual Info: H D 74A C 14/H D 74A C T14 • H e x Inverter Schmitt Trigger Description The HD74AC14/HD74ACT14 contains six logic in­ verters which accept standard CMOS input signals TTL levels for HD74ACT14 and provide standard CMOS output levels. They are capable of trans­

HD74AC139

Abstract: HD74ACT139 Hitachi DSA00348
Contextual Info: HD74AC139/HD74ACT139 Dual 1-of-4 Decoder/Demultiplexer Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low

Contextual Info: HD74AC158/HD74ACT158 D escription • Quad 2-Input Multiplexer Pin Assignment The H D 74A C 158/H D 74A C T158 is a high-speed quad 2-input m ultiplexer. It selects four bits of data from tw o sources using th e com m on Select and Enable inputs. T he four buffered o u tp u ts present

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Contextual Info: H D 7 4 A C 1 0 9 / H D 7 4 A C T 1 0 9 *r;“ho„Po’ ”Ed°”T,s»«*d Description The HD74AC109/HD74ACT109 consists of two high­ speed completely independent transition clocked JK flipflops. The clocking operaiton is independent of rise and fall times of the clock waveform. The JK design allows

74AC194

Contextual Info: HD74AC194/HD74ACT194 Description Pin Assignment T h is b id ire ctio n al shift register is designed to in co rp o ra te v irtu a lly all o f th e features a system designer m ay w ant in a shift register. It features p a ralle l inputs, p a ralle l outputs,

74AC181

Abstract: 74ACT181 004II 225si HD74AC181
Contextual Info: HD74AC181/HD74ACT181 Description Pin Assignment I-1-S ./ The H D 74A C 181/H D 74A C T181 is a 4-bit A rith­ m etic logic U nit ALU w hich can perform all the possible 16 logic operations on tw o variables and a variety o f arithm etic operations. • O u tputs Source/Sink 24 mA

Hitachi DSA00279

Contextual Info: HD74AC195 4-bit Parallel-Access Shift Register Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q0

HD74AC157

Abstract: Hitachi DSA00335
Contextual Info: HD74AC157 Quad 2-Input Multiplexer Description The HD74AC157 is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four outputs present the selected data in the true noninverted form. The HD74AC157 can also be used as a function generator.

HD74AC181

Abstract: HD74AC182 HD74AC381
Contextual Info: HD74AC182 Carry Lookahead Generator REJ03D0258–0200Z Previous ADE-205-378 (Z Rev.2.00 Jul.16.2004 Description The HD74AC182 is a high-speed carry lookahead generator. It is generally used with the HD74AC181 or HD74AC381 4-bit arithmetic logic unit to provide high-speed lookahead over word lengths of more than four bits.

HD74AC174

Abstract: HD74AC174FPEL HD74AC174RPEL
Contextual Info: HD74AC174 Hex D-Type Flip-Flop with Master Reset REJ03D0256–0200Z Previous ADE-205-376 (Z Rev.2.00 Jul.16.2004 Description The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a

HD74AC139AFPEL

Abstract: HD74AC139 HD74AC139AP HD74ACT139
Contextual Info: HD74AC139/HD74ACT139 Dual 1-of-4 Decoder/Demultiplexer REJ03D0249–0200Z Previous ADE-205-369 (Z Rev.2.00 Jul.16.2004 Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low outputs. Each decoder has an

HD74AC154

Contextual Info: HD74AC154/HD74ACT154 Description The HD74AC154/HD74ACT154 is a multipurpose decoder designed to accept four inputs and provide 16 mutually exclusive outputs. By means of the Address Ao—A3 inputs, data applied to one of the Enable inputs can be routed to any one of the

Contextual Info: HD74AC157 Quad 2-Input Multiplexer Description Pin Assignm ent The HD74AC157 is a high-speed quad 2-input m ulti­ plexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four o u tp u ts p r e s e n t th e se le c te d d a ta in th e tr u e

74AC157

Contextual Info: HD74AC157 • Quad 2-In p u t M ultiplexer Description Pin Awinnment The HD74AC157 is a high-speed quad 2-input multi­ plexer. Pour bits of data from two sources can be selected using the common Select and Enable inputs. The four o u tp u ts p re se n t th e selected d a ta in th e tru e

Contextual Info: H D 7 4 A C 1 3 3 /H D 7 4 A C T 1 3 8 .1 - o f - 8 Description The HD74AC138/HD74ACT138 is a high-speed l-of-8 decoder/demultipiexer. This device is ideal!y suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow

DECODER

Abstract: HD74AC138 HD74ACT138 Hitachi DSA00395
Contextual Info: HD74AC138/HD74ACT138 1-of-8 Decoder/Demultiplexer Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow

HD74AC175

Abstract: Hitachi DSA00395
Contextual Info: HD74AC175 Quad D-Type Flip-Flop Description The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the Low-toHigh clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset

HD74ACT161

Contextual Info: HD74ACT161 H D 74A C 163/H D74ACT163 Description Pin Assignment The HD74ACT161 and HD74AC163/HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count

DP-14

Abstract: HD74AC125 HD74AC125FPEL HD74AC125P HD74AC125RPEL HD74ACT125 hd74ac125tell
Contextual Info: HD74AC125/HD74ACT125 Quad Buffer/Line Driver with 3-State Output REJ03D0246–0300 Rev.3.00 Nov.12.2004 Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density.

HD74AC107

Abstract: HD74AC107FPEL HD74AC107RPEL HD74ACT107
Contextual Info: HD74AC107/HD74ACT107 Dual JK Flip-Flop with Separate Clear and Clock REJ03D0243–0200Z (Previous ADE-205-363 (Z) Rev.2.00 Jul.16.2004 Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the

HD74AC123A

Abstract: hd74ac123 Hitachi DSA00219
Contextual Info: HD74AC123A Dual Retriggerable Resettable Multivibrator ADE-205-365 Z 1st. Edition Sep. 2000 Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the

HD74AC181

Abstract: HD74AC182 HD74AC381 HD74ACT182 Hitachi DSA00219
Contextual Info: HD74AC182/HD74ACT182 Carry Lookahead Generator ADE-205-378 Z 1st. Edition Sep. 2000 Description The HD74AC182/HD74ACT182 is a high-speed carry lookahead generator. It is generally used with the HD74AC181 or HD74AC381 4-bit arithmetic logic unit to provide high-speed lookahead over word

HD74AC123A

Abstract: HD74AC123AFPEL HD74AC123AP hd74ac123 28 pin ic cd 1628
Contextual Info: HD74AC123A Dual Retriggerable Resettable Multivibrator REJ03D0245–0200Z Previous ADE-205-365 (Z Rev.2.00 Jul.16.2004 Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth