H JTAG Search Results

7400 series pinout diagram

Abstract: pin diagram 7400 series 7400 chip
Contextual Info: Features H H H H H H H H H H H H H H H H 18SPECint95, 16SPECfp95 @266Mhz w/1MB L2 @200Mhz 3.2 GFLOPS @ 400 MHz Peak performance Selectable bus clock (14 CPU bus dividers up to 9x) 7 selectable core to L2 frequency divisors Selectable interface voltage below 3.3 V (1.8 V, 2.5 V)

Contextual Info: User’s Manual 32 V850E/SJ3-H, V850E/SK3-H User’s Manual: Hardware RENESAS MCU V850E/Sx3-H Microcontrollers V850E/SJ3-H: PD70F3474A μPD70F3477A μPD70F3931B μPD70F3934B μPD70F3937B μPD70F3475A μPD70F3478A μPD70F3932B μPD70F3935B μPD70F3938B μPD70F3476A

MPC107

Abstract: PC107A PC7400
Contextual Info: Features H Processor bus frequency up to 100 MHz. H 64-bit or 32 bits data bus and 32-bit address bus. H Provides support for either asynchronous SRAM, burst SRAM, or pipelined burst SRAM. H Compliant with PCI specification, revision 2.1. H PCI interface operates up to 66 MHz/5.0 Volt compatible.

Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsys and Viewlogic H ig h C a p a c ity • JTAG 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

Transistor mcr 22-8 412

Contextual Info: O rd er U lis d a ta s h e e t b y H 4C /D MOTOROLA H4C SERIES SEMICONDUCTOR TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H PER FO R M A N C E T R IP L E LAYER M ETA L The s u b -m ic ro n H 4 C S eries'“ CM O S gate array family and the new

Contextual Info: Preliminary Data Sheet August 1998 microelectronics group Lucent Technologies Bell Labs Innovations Ambassador T8100 H.100/H.110 Interface and Time-Slot Interchanger 1 Product Overview Programmable switching between local time slots and H.100 bus, up to 256 connections

Contextual Info: VP2614 DS3735 - 3.2 VP2614 H.261 VIDEO DE-MULTIPLEXER Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 FEATURES DESCRIPTION • Fully integrated H.261 video de-multiplexer ■ Inputs an H.261 bitstream. Outputs error corrected run

B12C3

Abstract: LA1240
Contextual Info: Integrator Series FPGAs - 1200XL and 3200DX Familes F e a tu re s Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsys and Viewlogic H ig h C a p a c ity • JTAG 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM

H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S
Contextual Info: VP2614 VP2614 H.261 Video De-Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION • Fully integrated H.261 video de-multiplexer ■ Inputs an H.261 bitstream. Outputs error corrected run

H261

Abstract: VP2611 VP2612 VP2614 VP2615 VP510 VP520S
Contextual Info: VP2614 VP2614 H.261 Video De-Multiplexer Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION • Fully integrated H.261 video de-multiplexer ■ Inputs an H.261 bitstream. Outputs error corrected run

210W

Abstract: system on a chip 405A3
Contextual Info: PowerPC PoiverPC 44 5x3 Embedded Cores Low-cost, reusable, 200+ M H z cores fo r system on a chip applications 4 0 5 CPU H ig h lig h ts PowerPC 405x3 em be d d e d cores are 32-bit RISC cores for use in custom logic applications, as well as standard products from IBIVP. These em be d d e d

Contextual Info: g | M ITEL VP2614 H.261 Video De-Multiplexer SEM ICONDUCTOR Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3735 - 3.2 October 1996 FEATURES DESCRIPTION • Fully integrated H.261 video de-multiplexer ■ Inputs an H .261 bitstream. Outputs error corrected run

Contextual Info: Whp\ H EW LETT mLftM P A C K A R D Tachyon TL 33 MHz PCI to F ib re C h a n n e l C o n t r o ll e r Technical Data HPFC-5100C Fe atures • S eco n d G en eration C on troller IC, B a se d on H P ’s TACHYON F am ily A r c h ite c tu r e • S u p p o rts A ll F ib re C h an n el

CY3600

Abstract: tI11J CY37128P84-125JI
Contextual Info: fax id: 6146 ÆÊ PRELIMINARY F T V f S T “ ¡T * &*• risaliiJF ;UI Flmßbö Ultra37128 U ltraLogic 128-Macrocell IS R ™ CPLD H ig h s p e e d Features — • 128 m a c ro c e lls in e ig h t lo g ic b lo c k s f MAX = 167 M H z — t PD = 6.5 ns

powerpc 7xx dhrystone

Abstract: 401B2 STA 401
Contextual Info: PowerPC FmverFil 401 xZ Em bedded Cores Optimized low-cost cores utilizing IBM Blue Logic* technology H ig h lig h ts 401 CPU • Compatible with PowerPC User Instruction Set Architecture 84 MIPS Dhrystone 2.1 @ 80M Hz 3.1 mm2, in 0.35/j CMOS process, (.27/j Lgff), three levels of metal

infineon tricore

Abstract: TC1115 TC1130
Contextual Info: Product Brief TC1115 32-Bit Superscalar T r i C o r e TM A r c h i t e c t u r e T H E H I G H L Y I N T E G R A T E D T C 1 1 1 5 combines a Memory Management Unit MMU and a Floating Point Unit (FPU) on one chip. It is designed to meet the increasing performance, reliability and costs

Contextual Info: Advance Data Sheet February 1998 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations Ambassador T8100 H.100/H.110 Interface andTime-Slot Interchanger 1 Product Overview Programmable switching between local time-slots and H.100 bus, up to 256 connections

alps LCD

Abstract: Am386DE am486dx5 20 pin lcd connector and am386-dx 40 Am386DX interrupts of x86 microprocessor 20 pin lcd 80C186 programming rs232
Contextual Info: T H E E8 6 F A M I L Y AMD’s x86 Embedded Solutions AMD’s E86 family of x86 compatible devices provides the best price/performance value from the world’s dominant microprocessor architecture. > Industry standard x86 T H E VA L U E O F T H E WO R L D ’ S D O M I N A N T A R C H I T E C T U R E .

Contextual Info: P S G E C p l e s s e y DS3735 • 3.2 VP2614 H.261 VIDEO DE-MULTIPLEXER Supersedes version in June 1995 Digital Video & DSP 1C Handbook, HB3923-2 FEATURES DESCRIPTION • Fully integrated H.261 video de-multiplexer ■ Inputs an H.261 bitstream. Outputs error corrected run

dr25 diode specifications

Abstract: RTI Electronics C8051F220 C8051F022 dr 25 diode dr25 diode datasheet ir10 jtag sequence sample code read and write flash memory AN105
Contextual Info: AN105 P R O G R A M M I N G FLASH T H R O U G H T H E J TA G I N T E R F A C E Relevant Devices This application note applies to the following devices: C8051F000, C8051F001, C8051F002, C8051F005, C8051F006, C8051F010, C8051F011, C8051F012, C8051F015, C8051F016,

cstce8m00g1

Contextual Info: User’s Manual V850ES/SG2, V850ES/SG2-H 32-bit Single-Chip Microcontrollers Hardware V850ES/SG2: PD703260 μPD703260Y μPD703261 μPD703261Y μPD703262 μPD703262Y μPD703263 μPD703263Y μPD70F3261 μPD70F3261Y V850ES/SG2-H: μPD703262HY μPD703263HY μPD70F3263

LD011

Contextual Info: m i c r o e l e c t r o n i c s group Advance Data Sheet November 1997 Lucent Technologies Bell Labs Innovations Ambassador T8100 H.100/H.110 Interface andTime-Slot Interchanger 1. Product Overview • Programmable switching between local time-slots and H.100 bus, up to 256 connections

Contextual Info: Order this data sheet by H4C/D MOTOROLA H SEMICONDUCTOR “ TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H P ER FO R M A NC E T R IP L E LAYER M ETAL S U B -M IC R O N CMOS ARRAYS The s u b -m ic ro n H 4C S e rie s ’ " CM OS gate array fa m ily and th e new

Contextual Info: Preliminary XR-T7234 «/ E3 UNI User Network Interface 1C for ATM December 1997-1 FEATURES • APPLICATIONS C om pliant w ith U T O P IA Level 2 Interface Specification • S upports 8 or 16 Bit U T O P IA Bus O perating at 25M H z or 33M H z or 50M H z