GG14T Search Results

seven transistor drivers

Abstract: 251C M54524P WI54524P LF400
Contextual Info: b3E b24TflP7 GG14TflM 213 !•■ M I T B M ITSUBISHI BIPOLAR DIGITAL ICs M54524P MITSUBISHI DGTL LOGIC 7-UNIT 500mA DARLINGTON TRANSISTOR ARRAY W ITH CLAMP DIODE DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M54524P, 7-channel sink driver, consists of 14 NPN tran­

BUZ41A

Contextual Info: SILICONIX INC 1ÖE » • Ô2S473S O G m b Q T Ö BUZ41A fsr Siliconix in c o r p o r a t e d N-Channel Enhancement Mode Transistor TO-220AB TOP VIEW ~Ô~ PRODUCT SUMMARY V BR|DSS 'W 500 1.5 •d (A 4.5 1 GATE 2 DRAIN (Connected to TAB) 3 SOURCE ABSOLUTE MAXIMUM RATINGS (Tc = 25°C Unless Otherwise Noted)

A63A

Abstract: 74LSOO
Contextual Info: •Quadruple 2-input Positive AND Gates with Open Collector Outputs IP IN ARRANGEMENT ¡C IR C U IT S C H E M A T IC ^ ) •RECOM M ENDED OPERATING CONDITIONS Symbol min typ max High level output voltage Item VOH - - 5.5 Unit V Low level output current IOL

DIVIDE-BY-256

Abstract: ONU block diagram 74LSOO HD74LS393 a63a
Contextual Info: •D u a l 4-bit Binary Counters This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement tw o individual four-bit counters. The HD74LS393 comprises tw o independent four-bit binary counters each having a clear and a clock input.

74LSOO

Abstract: HD74LS490
Contextual Info: HD74LS490. This c irc u it d itio n a l contains gating to eigh t master-slave im p le m e n t tw o Dual 4 -b it Decade Counters flip -flo p s ind ividu al 4 -b it and ad ­ I BLOCK DIAGRAM K decade counters. Each decade c o u n te r has ind ividu al clo ck, clear, and

74LSOO

Abstract: HD74LS642 Hitachi Scans-001
Contextual Info: ♦ O c ta l Bus Transceivers inverted open-collector outputs This octal bus transceiver is designed fo r asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus de­ pending upon the level at the direction control (D IR ) input. The

74LSOO

Contextual Info: •Quadruple 2-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) BPIN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max High level output voltage y oh - - 5 .5 Low level output c u rre n t IO L - -

74LSOO

Abstract: CI 2210 HD74LSoop
Contextual Info: •T rip le 3-input Positive NOR Gates • C IR C U IT S C H E M A T IC ^ B P IN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 2 0 - +75°C ) Item S ym bol T e s t C o n d itio n s min typ* m ax V lH 2 .0 - - V lL - - 0 .8 U n it Input v o lta g e V

74LSOO

Abstract: 1S2074
Contextual Info: •Q u a d ru p le 2-input Positive N AND Schmitt-triggers •C IR C U IT S C H EM A TIC ^ HPIN ARRANGEMENT ■ELECTRICAL CHARACTERISTICS ( Ta= - 20- + 75”C ) Item Symbol min typ* max Unit Vt + V cc — 5V T e s t Conditions 1.4 1.6 1.9 V Vt ~ V cc — 5V

74LSOO

Abstract: HD74LS367A kl66
Contextual Info: HD74LS367A * Hex Bus Drivers non-inverted data outputs with three-state outputs I PIN ARRANGEMENT I CIRCUIT SCHEMATIC D r i v e r se c tio n (1 / 6 ) C o n t r o l se c tio n Ootpu Control Ci ~ï7 ]vVcc — 1Output Cont roi Ci 'vLLKy L jc t-E I 6 " Y r]D *

ATML U 010

Abstract: ATML H 010 1S2074 400M 74LSOO HD74LS139 OG-16 L400M ATML 010
Contextual Info: H D 74LS139. Dual 2-line-to-4-line Decoders/Demultiplexers IPIN ARRANGEMENT The H D74LS139 comprises two individual two-line-to-fourline decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications. IBLOCK DIAGRAM

HD74LSoop

Abstract: 1S2074 74LSOO HD74LS195A Hitachi Scans-001 Scans-0014928
Contextual Info: H D 74 L S 19 5A . 4-b¡t Parallel-Access Shift Registers This 4-bit register features parallel inputs, parallel outputs. is loaded into the associated flip-flop and appears at the out­ puts after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished

Contextual Info: •Quadruple 2-input High-voltage Interface Positive NAND Gates • C IR C U IT SC H EM A TIC O ^ B P IN ARRANGEMENT ■RECOM M ENDED OPERATING CONDITIONS Item S ym bol High lev e l o u tp u t v o lta g e Voh L ow lev el o u tp u t c u r r e n t min ty p

Contextual Info: •D u a l 4-input Positive AND Gates •PIN ARRANGEMENT ICIRCUIT SCHEMATICO^ ■ELECTRICAL CHARACTERISTICS Item Input voltage O utput voltage Symbol VlH VlL VOH V>L I ih It L ¡1 Input c u rren t S h o rt-c irc u it output c u rren t Supply c u rren t Input clam p voltage

1S2074

Abstract: 74LSOO HD74LS75 Hitachi Scans-001
Contextual Info: •Q uad ru ple Bistable Latches The H D 74LS75 is ideally suited for use as temporary storage for binary information between processing units and input/ • P IN ARRANGEMENT output or indicator units. Information present at a data D input is transferred to the Q output when the enable (G) is

HD74LS154

Abstract: 74LSOO ir 2210 ic LS2074
Contextual Info: •4-line-to-16-line Decoders/Demultiplexers This decoder utilizes T T L circuitry to decode four binarycoded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are low. The demul­ tiplexing function is performed by using the 4 input lines to

HD74LSoop

Abstract: 74LSOO 400M HD74LS54 Hitachi Scans-001
Contextual Info: •4 -w id e 2-input, 3-input AND-OR-INVERT Gates • C IR C U IT SCHEM ATIC B P IN ARRANGEMENT N ote The schem atic w ith in the dashed line is included the half inp ut term inals o f H D 7 4 L S 5 4 . ■ELECTRICAL CHARACTERISTICS T a = - 20- + 75°C )

74LSOOP

Abstract: 74LSOO
Contextual Info: HD74LS21 •D u al 4-input Positive AND Gates •PIN ARRANGEMENT ¡CIRCU IT SCHEMATICO^ ■ ELECTRICAL CH A RA CTERISTICS Item Symbol Input voltage VlL I6i IlH Input current IlL ¡1 Short-circuit output current Supply current Input clamp voltage * T est Conditions

DP 804 C

Abstract: JV3 diode 74LSOO HD74LS221
Contextual Info: HD74LS221 »Dual Monostable Multivibrators This multivibrator features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the tran­

74LSOO

Abstract: 74LSOO AND gate
Contextual Info: •Quadruple 2-input Exclus¡ve-OR Gates with open collector outputs • P IN ARRANGEMENT ■FUNCTION TABLE Output Inputs Y A B L L L L H H H L H H H L H ; high level, L ; low level, X ; irrelevant. ■RECOMMENDED OPERATING CONDITIONS Symbol min typ max

74LSOO

Abstract: HD74LS390 Hitachi Scans-001
Contextual Info: • Dual Decade Counters I BLOCK DIAGRAM {'A This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement two individual four-bit counters. The H D 74LS390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement cycle

HD74LSoop

Abstract: 74LSOO
Contextual Info: •D u a l 4-input Positive NAND Gates with Open Collector Outputs •C IR C U IT S C H E M A T IC ^ ) « P IN ARRANGEMENT ■RECOMMENDED OPERATING CONDITIONS Item High level output voltage Low leve) output current Symbol min - VoH ÌO L ■ELECTRICAL CHARACTERISTICS (

HD74LSoop

Contextual Info: H D 74L S 164 • 8 - B it Parallel-Out Serial-ln Shift Registers IP IN ARRANGEMENT This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs A and B permit complete control over incoming data as a low at either (or

D74LS175

Abstract: 74LS174 example S174H HD74LSoop 74ls175
Contextual Info: H D 74LS174/H D74LS175 •H e x Quadrupte D-type Rip-Hops with clear IBLOCK DIAGRAM These positive-edge-triggered flip-flops utilize T T L circuitry to implement D-type flip-flop logic. A ll have a direct clear input, and the H D74LS175 features complementary outputs