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GATEFIELD Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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ESBGA
Abstract: Star Sea Electronics OA21 micro power intellect 391-Pin Electromec Zycad
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GF250F GF250FTM GF200F GF200F, GF250F, ESBGA Star Sea Electronics OA21 micro power intellect 391-Pin Electromec Zycad | |
lm 7803
Abstract: gmob thesis
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ED-44, ESSDERC2000, lm 7803 gmob thesis | |
scr 122Contextual Info: ASICmaster ä User’s Guide Windows NT ä and UNIX ® Environments Actel Corporation, Sunnyvale, CA 94086 1999 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579018-0 Release: November 1999 No part of this document may be copied or reproduced in any form or by |
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Contextual Info: uture is bright the future is bright the future is bright the future is bright the future is bright the future is bright the futur ght the future is bright the future is bright the future is bright the future is bright the future is bright the future is bright t |
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OB33LN
Abstract: IOB33LNU IOBL33LLU OB25LPLL IOBL25HHU OB33PL IOB33PH OTB33PL OB33LL
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IB33U IB25U IB25LPU IB25LP OB33LN IOB33LNU IOBL33LLU OB25LPLL IOBL25HHU OB33PL IOB33PH OTB33PL OB33LL | |
ersa 111
Abstract: asynchronous fifo design in verilog GF260F180-C391C-4 WaCS Gatefield 10R1W
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GF260F GF260FTM GF250F GF26oASIC, ersa 111 asynchronous fifo design in verilog GF260F180-C391C-4 WaCS Gatefield 10R1W | |
Contextual Info: Actel’s ProASIC Family The Nonvolatile Reprogrammable Gate Array • Nonvolatile and Reprogrammable • Low Power Consumption • Flexible Embedded User Memory -Built in FIFO Control Logic • ASIC-like Design Flow -Easy Timing Closure -Familiar Design Tools |
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200MHz | |
Contextual Info: Advanced v.2 ProASICTM 500K Family Features and Benefits • High Capacity • 98,000 to 1.1 Million System Gates • 14K to 138K Bit of Two-Port SRAM • 210 to 623 User I/Os • Performance • Corner-to-Corner Delay < 4 ns Typical • Clock-to-Out < 7 ns |
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200MHz | |
pioneer sx 1050
Abstract: implementation of apb in verilog
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A500K
Abstract: A500K270
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silicon sculptor
Abstract: 6 pin JTAG header
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A500K050
Abstract: A500K130 IB33U
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AC144 A500K130BG456; A500K050 A500K130 IB33U | |
FIFO256X9SSRP
Abstract: iob25hh RAM256X9AA
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IB33U
Abstract: S148
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A500K130BG456; IB33U S148 | |
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iob25hhContextual Info: ProASIC Macro Library Guide June 1999 Actel Corporation, Sunnyvale, CA 94086 ã 1999 Actel Corporation. All rights reserved. Part Number: 5579016-0 Release: June 1999 No part of this document may be copied or reproduced in any form or by any means without prior |
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Contextual Info: Actel’s ProASIC Family The Only ASIC Design Flow FPGA • ASIC-like Design Flow -Easy Timing Closure -Familiar Design Tools • Nonvolatile and Reprogrammable • Low Power Consumption • Flexible Embedded User Memory -Built in FIFO control logic • JTAG/IEEE 1149.1 Compliant |
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200MHz | |
Contextual Info: Actel Tools PinEdit User’s Guide R1-2002 Windows ® & UNIX ® Environments Actel® Corporation, Sunnyvale, CA 94086 2002 Actel Corporation. All rights reserved. Part Number: 5029119-3 Release: May 2002 No part of this document may be copied or reproduced in any form or by any |
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R1-2002 | |
ALUS-DContextual Info: ProASIC Interface Guide Windows and UNIX® Environments Actel Corporation, Sunnyvale, CA 94086 1999 Actel Corporation. All rights reserved. Printed in the United States of America Part Number: 5579014-0 Release: November 1999 No part of this document may be copied or reproduced in any form or by |
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Contextual Info: Actel’s ProASIC Family The Non-Volatile Reprogrammable Gate Array The Flash Advantage FLASH SWITCH WORD LINE SEL 1 SEL 2 Low Power Along with the high performance comes less power consumption. With the inherent efficiency of the routing structure and the architecture of the |
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200MHz | |
AC142
Abstract: IOB33PH IOB33PNU OTB33PL IOB33LL ob33lh OTB33PH
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AC142 AC142 IOB33PH IOB33PNU OTB33PL IOB33LL ob33lh OTB33PH | |
connector 2*5 ,RA jtag actelContextual Info: A ppl i cati on N ot e In-System Programming ProASIC 500K Devices with Silicon Sculptor In t ro d u c t i o n Design engineers today are increasingly required to work in a problem-free development and manufacturing environment to achieve success. To do this, designers often |
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20549
Abstract: unisys
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PD-2000-1Contextual Info: UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 10-Q Mark One QUARTERLY REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 For the quarterly period ended October 3, 1999 OR TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE |
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r 908
Abstract: "network interface cards"
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