FUNCTION OF X- OR GATES Search Results

82S153

Abstract: PLS153 24 SIGNETICS 82S153A/BRA Programmable Logic Array 2 input ex-or gate 14 pin ic 82S153A PLS153A fusible chip resistor pls153a jedec
Contextual Info: Product specification S ign etics Program m able L o gic Prod ucts Field programmable logic array 18 x 42 x 10 DESCRIPTION LOGIC FUNCTION • 10 OR gates The 82S153A is a two-tevel logic element, consisting of 42 AND gates and 10 OR gates with fusible link connections for programming

54LS32

Abstract: L032
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 04/22/98 Last Update Date: 06/16/98 Last Major Revision Date: 04/22/98 MNDM54LS32-X REV 1A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which perform the logic OR function.

Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 06/25/97 Last Update Date: 07/08/97 Last Major Revision Date: 06/25/97 CN54F32-X REV 0A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.

54F32LMQB

Abstract: 54F32 54F32DMQB 54F32FMQB MN54F32-X
Contextual Info: MILITARY DATA SHEET Original Creation Date: 03/12/96 Last Update Date: 07/30/96 Last Major Revision Date: 03/12/96 MN54F32-X REV 1A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.

54F32DMQB

Contextual Info: Nationa l Semiconductor MILITARY DATA SHEET Original Creation Date: 03/12/96 Last Update Date: 07/30/96 Last Major Revision Date: 03/12/96 MN54F32-X REV 1A0 QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.

GD74F08

Contextual Info: PRELIMINARY DATA SHEET GD74F08 QUAD 2-INPUT AND GATE Description This device contains four independent 2input AND gates, each of which performs the Boolean functions Y = A»B or Y = A+B. Function Table each gate Inputs Outputs A B Y H H H L X L X L L X Im m a te r ia l

Contextual Info: National Semiconductor MICROCIRCUIT DATA SHEET Original Creation Date: 12/06/96 Last Update D a t e : 06/19/97 Last Major Revision D a t e : 12/06/96 CN74F32-X REV OBO QUAD 2-INPUT OR GATE General Description This device contains four independent gates, each of which performs the logic OR function.

xor IC

Abstract: MOTOROLA ECL IC of XNOR GATE
Contextual Info: 'O' SY N E R G Y QUINT 2-INPUT 3Y10E1Û7 < O R / X N O R GA T E Y 10 R E i 0 7 S E M IC O N D U C T O R D E S C R IP TIO N FEATURES • ■ ■ ■ ■ 600ps max. propagation delay Extended 100E Vee range of -4.2V to -5.5V True and complementary outputs OR/NOR function outputs

schmitt trigger 4093

Abstract: D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable
Contextual Info: Revised April 1999 Functional Selection Table 1999 Fairchild Semiconductor Corporation MS500117.prf www.fairchildsemi.com Functional Selection Table February 1998 Gates Function CROSSVOLT Device Leads FACT FAST FASTr ALS AS LS S TTL ABT VCX LCX LVX LVT LVQ AC ACT

MIL-STD-806

Abstract: 5 inputs OR gate truth table 4 inputs OR gate truth table 6 inputs OR gate truth table truth table for 7 inputs OR gate SCHMITT INVERTER 6 inputs NOR gate truth table M1C21 demultiplexer truth table truth table for 4 inputs OR gate
Contextual Info: [4] Logic Symbols and Truth Tables [ 4 ] Logic Symbols and Truth Table 1. How to Read MIL-Type Logic Symbols Table 1.1 shows the MIL-type logic symbols used for high-speed CMOS ICs. This logic chart is based on MIL-STD-806. The clocked inverter and transmission gates have specific symbols.

DM74AS881BNT

Contextual Info: 881B O T National Semiconductor DM74AS881B 4-Bit Arithmetic Logic Unit/Function Generator General Description Features The DM74AS881B is an arithmetic logic unit ALU /function generator that has a complexity of 77 equivalent gates, re­ spectively, on a monolithic chip. These circuits perform 16

NC7SP57

Abstract: NC7SP57L6X NC7SP57P6X NC7SP58 NC7SP58L6X NC7SP58P6X
Contextual Info: Preliminary Revised November 2001 NC7SP57 • NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power (ULP) Series of TinyLogic. Each device is capable

Contextual Info: Preliminary Revised October 2001 NC7SP57 • NC7SP58 TinyLogic ULP Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Ultra Low Power (ULP) Series of TinyLogic. Each device is capable

Contextual Info: Preliminary Revised October 2001 NC7SP57 • NC7SP58 TinyLogic Universal Configurable 2-Input Logic Gates Preliminary General Description The NC7SP57 and the NC7SP58 are Universal Configurable 2-Input Logic Gates from Fairchild’s Super Low Voltage Series of TinyLogic. Each device is capable of being

HG62F

Abstract: V/HG62F HG62F43
Contextual Info: #U 210 HG62F SERIES Hitachi CMOS Gate Array High I/O to Gate Ratio JANUARY, 1990 0 H IT A C H I The F series consists of 6 masterslices ranging from 2,178 to 10,076 available gates with high I/O pin counts ranging from 136 pins to 208 pins. The HG62F series is a mastersliced gate array fabricated on 1.0

THERMAL Fuse m20 tf 115 c

Abstract: SX v3.1 REQ64 A54SX08 A54SX16 A54SX32 PAR64 313 pin PBGA fq1200 THERMAL Fuse l20 tf 115 c
Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

Contextual Info: v3.2 SX Family FPGAs u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out Pin-to-Pin 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates

Contextual Info: Advance Data Sheet February 1993 £ = — AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA Series Field-Programmable Gate Arrays Features • High density: 3500 to 22,000 usable gates ■ High I/O: up to 288 usable I/O ■ High performance: 80 MHz system clock rate

AM2019

Abstract: 2-bit half adder layout AX253 AX201 AM2001 AX261
Contextual Info: * Am3525 Mask-Programmable Gate Array With ECL RAM PRELIMINARY > 3 DISTINCTIVE CHARACTERISTICS • • • Up to 3718 equivalent gates - 416 internal cells - Up to 135 l/O s 1152 bits of ECL RAM 1K with byte-wide parity - Worst case T a a (access time) = 5.5 ns

Contextual Info: Product specification Philips Semiconductors Programmable Logic Devices Programmable logic sequencer 16x48x8 PLUS105-45 DESCRIPTION FEATURES The PLUS105-45 is a bipolar programmable state machine of the Mealy type. Both the AND and the OR array are userprogrammable. All 48 AND gates are

cd4558

Abstract: CD4087 CD4030A CD4062 CD4006A CD4057 CD4046A cd4020a 4016a CD40108B
Contextual Info: Product Classification Chart GATES Single-Level NOR/NAND C04OOOB CD4012B CD4012UB CD4012A CD4023B C04023UB CD4023A CD402SB C04025UB CD402SA CD4068B CD4078B CD40107B C04000UB C 04000A CD4001B CD4001UB CD4001A CD4002B CD4002UB CD4002A CD4011B CD4011UB CD4011A

full adder circuit using nor gates

Abstract: full adder circuit using xor and nand gates XC4005E/XL XC5000 figure of full adder circuit using nor gates circuit diagram of full adder circuit using nor XC4025E XC4000 XC4003E XC4006E
Contextual Info: APPLICATION NOTE Gate Count Capacity Metrics for FPGAs  XAPP 059 Feb. 1, 1997 Version 1.1 Application Note Summary Three metrics are defined to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. The methodology used to determine these values is described.

NC7SV57

Abstract: NC7SV57L6X NC7SV57P6X NC7SV58 NC7SV58L6X NC7SV58P6X
Contextual Info: Revised June 2002 NC7SV57 • NC7SV58 TinyLogic ULP-A Universal Configurable 2-Input Logic Gates General Description Features The NC7SV57 and NC7SV58 are universal configurable 2-input logic gates from Fairchild’s Ultra Low Power ULP-A Series of TinyLogic. ULP-A is ideal for applications

NC7SV57

Abstract: NC7SV57P6X NC7SV58 NC7SV58L6X NC7SV58P6X NC7SV57L6X 2-input XOR using 4 2-input NAND gates mark v58 NC7SV57P6
Contextual Info: Revised January 2003 NC7SV57 • NC7SV58 TinyLogic ULP-A Universal Configurable 2-Input Logic Gates General Description Features The NC7SV57 and NC7SV58 are universal configurable 2-input logic gates from Fairchild’s Ultra Low Power ULP-A Series of TinyLogic. ULP-A is ideal for applications that require extreme high speed, high drive and low