DM74S Search Results

TLO6

Abstract: 74S242 74S243 S243 74S242N
Contextual Info: DM 54S242/ DM 74S242. DM54S243/DM74S243 Quadruple Bus Transceivers General Description Absolute Maximum Ratings Note d These four data line transceivers are designed for asyn­ chronous two-way communications between data buses. They can be used to drive terminated lines down to 133

DM74S22

Contextual Info: DM54S22/DM74S22 National Semiconductor DM54S22/DM74S22 Dual 4-Input NAND Gates with Open-Collector Outputs General Description Absolute Maximum Ratings Note 1 T h is d e v ic e c o n ta in s fo u r in d e p e n d e n t g a te s e a ch o f w h ic h p e rfo rm s th e lo g ic N A N D fu n c tio n . T h e ope n c o lle c to r o u tp u ts re q u ire e x te rn a l p u ll-u p re s is to rs fo r

DM74S74N

Abstract: DM54S74W DM74S74 DM54S74J DM74S74M J14A M14A N14A W14B
Contextual Info: DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the

Contextual Info: S240 • S241 • S244 National Sem iconductor DM54S240/DM74S240, DM54S241/DM74S241, DM54S244/DM74S244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers General Description These buffers/line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers/

DM74S51

Abstract: DM74 DM74S51N N14A
Contextual Info: DM74S51 Dual 2-Wide 2-Input AND-OR-INVERT Gates General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Connection Diagram Dual-In-Line Package DS006454-1 Order Number DM74S51N

DM74S112

Abstract: DM54S112 DM54S112J DM74S112N J16A N16E
Contextual Info: DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs sition time of the negative going edge of the clock pulse. Data on the J and K inputs can be changed while the clock is high or low without affecting the outputs as long as setup

Contextual Info: S E M IC O N D U C T O R tm DM74S138, DM74S139 Decoders/Demultiplexers General Description These S chottky-clam ped circuits are designed to be used in high-perform ance m em ory-decoding o r data-routing a pplica­ tions, requiring very short propagation delay tim es. In

DM74S40

Abstract: DM74S40N MS-001 N14A
Contextual Info: DM74S40 Dual 4-Input NAND Buffer August 1986 Revised April 2000 DM74S40 Dual 4-Input NAND Buffer General Description This device contains two independent gates each of which performs the logic NAND function. Ordering Code: Order Number DM74S40N Package Number

DM74S32

Abstract: MS-001 N14A
Contextual Info: Revised April 2000 DM74S32 Quad 2-Input OR Gate General Description This device contains four independent gates each of which performs the logic OR function. Ordering Code: Order Number DM74S32 Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, 0.300 Wide

DM74S240

Abstract: DM74S240N DM74S241 DM74S241N DM74S244 DM74S244N S240
Contextual Info: EM ICONDUCTO R t DM74S240, DM74S241, DM74S244 Octal 3-STATE Buffer/Line Driver/Line Receiver H ysteresis at d ata inputs im proves noise m argins General Description Typical Iq l sink current 74S 64 mA These buffers/line drivers are designed to im prove both the

DM74S140

Abstract: MS-001 N14A
Contextual Info: Revised April 2000 DM74S140 Dual 4-Input NAND 50Ω Line Driver General Description This device contains two independent line driver gates each of which performs the logic NAND function. Ordering Code: Order Number DM74S140 Package Number N14A Package Description

AX2036

Contextual Info: R C H I I - D S E M IC O N D U C T O R tm DM74S03 Quad 2-Input NAND Gates with Open-Collector Outputs W here: General Description l OH = total m axim um output high current fo ra li outputs tied to pull-up resistor This device contains fo u r independent gates each of which

Contextual Info: S E M IC O N D U C T O R tm DM74S51 Dual 2-Wide 2-Input AND-OR-INVERT Gates General Description This device contains tw o independent com binations of gates each of w hich perform s th e logic A N D -O R -IN V E R T function. Connection Diagram Dual-ln-Line Package

Contextual Info: S194 National Semiconductor DM54S194/DM74S194 4-Bit Bidirectional Universal Shift Registers Shift right is accomplished synchronously with the rising edge of the clock pulse when SO is high and S1 is low. Serial data for this mode is entered at the shift-right data

Contextual Info: National Æii Semiconductor DM54S20/DM74S20 Dual 4-Input NAND Gates General Description This device contains two independent gates each of which performs the logic NAND function. Connection Diagram Dual-ln-Une Package C2 NC B2 Tl/F/6449-1 Order Number DM54S20J, DM54S20W or DM74S20N

Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74S05 Hex Inverters with Open-Collector Outputs W here: General Description N-, lOH = total m axim um output high current fo r all outputs tied to pull-up resistor This device contains six independent gates each o f which

Contextual Info: S E M I C O N D U C T O R tm DM74S133 13-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Connection Diagram Dual-ln-Line Package Vcc M L K J I H Y DS006462-1 Order Number DM54S133J, DM74S133M or DM74S133N

74s112n

Abstract: 54S112 74S112
Contextual Info: I R C H I L D S E M I C O N D U C T O R TM DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description sition tim e of th e negative going edge o f the clock pulse. Data on the J and K inputs can be changed w hile the clock

Contextual Info: R C H II_ D E M IC O N D U C T O R t DM74S157, DM74S158 Quad 1 of 2 Line Data Selectors/Multiplexers • S ource program m able counters General Description These d ata selectors/m ultiplexers contain inverters and d riv­ ers to supply full on-chip d ata selection to the four output

Contextual Info: S E M IC O N D U C T O R tm DM74S253 Dual 3-STATE 1 of 4 Line Data Selectors/Multiplexers S chottky-diode-clam ped transistors General Description Each of these S chottky-clam ped data selectors/m ultiplexers contains inverters and drivers to supply fu lly com plem entary,

902 FAIRCHILD

Contextual Info: •M ICO N DUCTO R r DM74S240, DM74S241, DM74S244 Octal 3-STATE Buffer/Line Driver/Line Receiver Hysteresis a t d ata inputs im proves noise m argins General Description Typical iOL sink current 74S 64 mA These buffers/line drivers are designed to im prove both the

Contextual Info: S E M IC O N D U C T O R tm DM74S20 Dual 4-Input NAND Gates General Description This device contains tw o independent gates each of which perform s the logic NAND function. Connection Diagram Dual-ln-Line Package V rC 02 C2 13 I . NC 12 B2 |l1 A2 10 Y2 9 8

Contextual Info: DM54S22/DM74S22 2 National Sem iconductor DM54S22/DM74S22 Dual 4-Input NAND Gates with Open-Collector Outputs General Description Absolute Maximum Ratings Note 1 This device con tains fo u r independent gates each o f w hich perform s the logic NAND fun ction. The openc o lle c to r ou tputs require external pull-up resistors for

74S133

Abstract: DM74S133 DM74S133M DM74S133N M16A MS-001 N16E 13-INPUT
Contextual Info: Revised April 2000 DM74S133 13-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Ordering Code: Order Number Package Number Package Description DM74S133M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, 0.150 Narrow