74ALS00A Search Results

MS-012-AB

Abstract: TEXTOOL zif dip socket TEXTOOL zif socket 74ALS 74ALS00A 74ALS00AD 74ALS00AN SOL-24 3BTI
Contextual Info: Signetics 74ALS00A Quad 2-Input NAND Gates Product Specification ALS Products FUNCTION TABLE INPUTS OUTPUT A B T Y P IC A L P R O P A G A T IO N D E LA Y TY P E 4 .0 ns 74A LS00A T Y P IC A L S U P P L Y C U R R E N T T O T A L 1 .0 m A Y H H L L X H X

Philips Semiconductors Selection Guide

Abstract: 74ALS08
Contextual Info: Philips Semiconductors Functional selection guide GATES FUNCTION INVERTERS NAND NOR DEVICE NUMBER NUMBER OF PINS Hex inverters 74ALS04B 14 Quad 2-input 74ALS00A 14 Triple 3-input 74ALS10A 14 Dual 4-input 74ALS20A 14 8-input 74ALS30A 14 Quint 2-input NAND, open collector

Contextual Info: Philips Sem iconductors Product specification Quad 2-input NAND gate TYPE 74ALS00A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 4.0ns 1,0mA PIN CONFIGURATION K J 1A [ T 74ALS00A ORDERING INFORMATION O RDER CODE CO M M E R C IA L RANGE V cc = 5V ±10%,

Octal to binary

Abstract: OCTAL D-TYPE LATCH NON-INVERTING 74ALS08 octal inverter
Contextual Info: Section 2 Advanced Low-power Schottky Logic ALS CONTENTS 74ALS00A Quad 2-input NAND gate . 31 74ALS02 Quad 2-input NOR gate .

SOT27-1 DIP14

Abstract: 74ALS 74ALS00A 74ALS00AD 74ALS00ADB 74ALS00AN
Contextual Info: INTEGRATED CIRCUITS 74ALS00A Quad 2-Input NAND gate Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Quad 2-input NAND gate TYPE 74ALS00A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT

74ALS

Abstract: 74ALS00A 74ALS00AD 74ALS00AN
Contextual Info: 74ALS00A Quad 2-Input NAND Gates Product Specification FUNCTION TABLE OUTPUT INPUTS A B 4 .0 ns 74A LS00A 1 .0 m A 7 H H L L X H X L H NO TES: H = High voltage level L = Low voltage level X = Don't care T Y P IC A L S U P P L Y C U R R E N T T O T A L T Y P IC A L P R O P A G A T IO N

Contextual Info: Philips Semiconductors Product specification Quad 2-input NAND gate TYPE 74ALS00A TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 4.0ns 1.0mA 74ALS00A PIN CONFIGURATION 1A (T ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE Vc c = 5V ±10%, Tamb = 0°C to +70°C

54ALS00A

Abstract: SN54ALS00A SN54AS00 SN74ALS00A SN74AS00 ALS00a texas instruments 1at
Contextual Info: C t 1 SN54ALS00A, SN54AS00, 74ALS00A, SN74AS00 QUADRUPLE 2 INPUT POSlTIVE-NAND GÄtES D 2 6 6 1 , APRIL 1 9 8 2 -R E V IS E D M A Y 198 6 S ty 5 4 4A L S 0 0 A , S N 5 4 A S 0 0 . . . J P AC K A G E |J74ÀL£|OOA, S N 7 4 A S 0 0 . . . D OR N PAC KA G E

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1035P TËJ MITSUB ISH I {DGTL LOGIC} Q012732 G | HEX NONINVERTING BUFFER W ITH OPEN COLLECTOR OUTPUT / DESCRIPTION PIN CONFIGURATION TOP VIEW ” T h e M 7 4 A L S 1 0 3 5 P is a s e m ic o n d u c to r in te g ra te d c ir­ c u it c o n s is tin g o f six n o n -inverting b u ffe rs w ith open

ci la 7610

Contextual Info: c +e MITSUBISHI ALSTTLs . op,00° M 74A L S 620A -1P v ie N v t ^s ^ - 3 _ OCTAL BUS TRANSCEIVER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI CDGTL LOGIC) DESCRIPTION The M74ALS6Í20A-1P is a semiconductor integrated cir­ cuit consisting of eight bus transm itter/receiver circuits

ci la 7610

Contextual Info: MITSUBISHI ALSTTLs M 7 4 A LS 6 5 1 P 7 -52-3/ OCTAL BUS TRANSCEIVER/REGISTER W ITH 3-STATE OUTPUT INVERTED 6249827 MITSUBISHI 91 D 12674 (DGTL LOGIC ) DESCRIPTION The M74ALS651P is a semiconductor integrated circuit consisting of eight bus transceiver/registers with 3-state

Contextual Info: MITSUBISHI íDGTL LOGICI TI DEI't.E4*1ñ27 D0ia3flD S MITSUBISHI ALSTTLs M 624 9 82 7 M IT S U B IS H I DG TL L O G IC 7 4 A 91D L S 1 1 3 A P 12380 D DUAL J-K N EG A TIVE EDGE-TRIGGERED FLIP -FLO P W IT H SET T -H (* -o 7 -o y DESCRIPTION PIN CONFIGURATION (TOP VIEW)

m74als191p

Contextual Info: ÍDGTL LOGIC} 91D TI De | 12446 b241fl27 □ 0 1 2 4 4b ñ r D MITSUBISHI ALSTTLs M 74A LS191P SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER W ITH MODE CONTROL • 7 ^ V ' 5 ' ' ^ >3 DESCRIPTION - o 7 PIN CONFIGURATION TOP VIEW Th e M 7 4 A L S 1 9 1 P is a s e m ic o n d u c to r in te g ra te d c irc u it

74ALS640

Contextual Info: MITSUBISHI -CDGTL LOGIC} dT | ba^flS? D O i a k b B 4 M ITSUBISHI A L ST T Ls sc* -s s 5 " : . M 7 4 A LS6 4 7 P ,o.9B OCTAL BUS TR A N SC EIV ER /R EG IST ER WITH OPEN COLLECTOR OUTPUT NONINVERTED 6249827 MITSUBISHI CDGTL LOGTC) DESCRIPTION The M74ALS647P is a semiconductor integrated circuit

J 5027 R

Abstract: BEM 6K
Contextual Info: MIT SUBISH I íDGTL L O G I C } T I d ËT| ^5^027 ~JZ.SZt~3/ G0127SS □ MITSUBISHI ALSTTLs M 74A L S 1621A P I 62 49 8 2 7 M I T S U B I S H T T D G T L T o G r ^ ~ 910 12755 D OCTAL BUS TRANSCEIVER W ITH OPEN COLLECTOR OUTPUT NONINVERTED) DESCRIPTION

Contextual Info: MITSUBISHI -CDGTL L O G I O TI DE | bSMTfla? 001E4b4 □ M IT SU B ISH I ALSTTLs M74ALS241AP 6249827 MITSUBISHI DGTL LOGIC 91D 12464 D O CTAL B U F F E R /L IN E D R IV E R W IT H 3 -ST A T E O U T PU T (N O N IN V E R T E D ) DESCR IPTIO N The M74ALS241AP is a semiconductor integrated circuit

Contextual Info: MITSUBISHI ALSTTLs & M74ALS169BP T ' - v ’S '- J J - o SYNCHRONOUS PRESETTABLE UP/DOWN 4 -B IT BINARY COUNTER 6249827 MITSUBISHI DG TL LOGIC DESCRIPTION Th e M 74A L S 169 B P is a sem iconductor integrated circuit of a synchronous p resettable u p /d o w n

74als561

Contextual Info: MITSUBISHI íDGTL LOGIC} "DÌI bSMTñE? 00123ki7 5 TI W~ M IT S U B IS H I* !L. S T T L s M74ALS38AP 91D 12367 D 6249827 MITSUBISHI DGTL LOGIC QUADRUPLE 2 -IN P U T P O S ITIV E NAND BUFFER W IT H OPEN COLLECTOR OU TPUT T - - V 3 - / S DESCRIPTION PIN CONFIGURATION (TOP VIEW)

Contextual Info: "d ë J M ITS UBISHI -CDGTL L O G I O bEMTfla? ooiBS'in a S^Ls MITSUBISHI ALSTTLs M 74ALS133P r _ 6249827 MITSUBISHI - y j - / r SINGLE 13-IN PU T POSITIVE NAND GATE DGTL LOGIC DESCRIPTION Th e M 7 4A LS 133P is a sem iconductor integrated circuit

m74als

Abstract: M74ALS109AP 74ALS640
Contextual Info: M IT S U B IS H I {D G T l T o G IcT ^ I b H 1 SS? M 6249827 MITSUBISHI 7 4 A CDGTL LOGIC 91D J STTLs L S 1 0 9 A 12 37 4 P D DUAL J-R POSITIVE EDGE-TRIGGERED FLIP-FLOP W ITH SET AND RESET T -V & -0 7 - Ô ? DESCRIPTION PIN CONFIGURATION TOP VIEW) The M74ALS109AP is a semiconductor Integrated circuit

gt 568

Abstract: m74als568ap m74als568a
Contextual Info: MITSUBISHI -CDGTL L O G I O de! TI tsMiaa? QGiasai 4 |~~ M IT S U B IS H I ALSTTLs ~ J- M 74A LS 568A P S Y N C H R O N O U S P R E S E T T A B L E U P /O O W N D EC A D E C O U N TE R _ W IT H 3 -S T A T E O U T P U T 1H249827 MITSIJBISHI

M74ALS1032AP

Contextual Info: MITSUBISHI ALSTTLs M 74ALS1 0 3 2 AP M I T S U B I S H I - C D G T L L O G I C } T I D È I ” L ^ M ^ ñ S ? 1 2 7 5 fi QUADRUPLE 2-IN P U T POSITIVE OR BUFFER _ DESCRIPTION _ _ _ _ PIN CONFIGURATION TOP VIEW The M74ALS1032AP is a semiconductor integrated cir­

74AS00

Abstract: 74ALS00AM
Contextual Info: TYPES SN54ALS00A, SN54AS00, SN74ALSQ0A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D D E C E M B E R 1 9 8 3 I• Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic D IPs

74ALS573AD

Abstract: 74ALS574AD
Contextual Info: M ITSUBISHI ALSTTLs r M 7 4 A L S 1 6 4 5 A P D e | bSMTfla? DDia77T 3 MITSUBISHI -CDGTL LOGIC} OCTAL BUS TR A N SC EIVER W IT H 3-STATE O U TPUT N O N IN VERTED - 7 “' » DESCRIPTION The M74ALS1645AP is a semiconductor integrated cir­ cuit consisting of eight bus transmitter/receiver circuits