FOUR INPUT NAND GATE Search Results

DM54L00J

Contextual Info: DM54L00 DM54L00 Quad 2-Input NAND Gates Literature Number: SNOS264A DM54L00 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Connection Diagram Function Table Dual-In-Line Package

ACT132

Contextual Info: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2−input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter−free output signals. In addition, they have greater noise margin than conventional NAND gates.

74ac132

Abstract: 74ACT132 ACT132 MC74AC132 MC74AC132D MC74AC132DR2 MC74AC132N MC74ACT132 MC74ACT132D MC74ACT132DR2
Contextual Info: MC74AC132, MC74ACT132 Quad 2-Input NAND Schmitt Trigger The MC74AC/74ACT132 contains four 2–input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter–free output signals. In addition, they have greater noise margin than conventional NAND gates.

LS132

Abstract: T54LS24D2
Contextual Info: PRELIMINARY DATA QUAD 2-INPUT SCHMITT TRIGGER NAND GATE DESCRIPTION The T54LS24/T74LS24 contains four 2-input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are ca­ pable of transforming slowly changing input signals

Contextual Info: M M O T O R O L A M C74AC132 M C74A C T132 Quad 2-Input NAND S ch m itt Trigger QUAD 2-INPUT NAND SCHMITT TRIGGER The MC74AC/74ACT132 contains four 2-input NAND gates which are capable of transforming slowly changing input signals into sharply defined, jitter-free output

ic 74132

Abstract: f 74132 LS132 74132 853051 R/ls 74132
Contextual Info: 74132, LS132 SigneHcs Schmitt Triggers Quad 2-Input NAND Schmitt Trigger Product Specification Logic Products The '132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming

DM74LS132

Abstract: DM74LS132M DM74LS132N DM74LS132SJ M14A M14D MS-001 N14A
Contextual Info: Revised March 2000 DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Input General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a

Contextual Info: AVG DDi Semiconductors Technical Data DV74LS03 DV74ALS03B Quad 2-Input NAND Gate with Open-Collector Outputs This device contains four independent 2-input NAND buffers, each of which performs the logic NAND function in positive logic. The open-collector outputs require pull-up resistors to

74F132

Abstract: 74F132PC 74F132SC 74F132SJ F132 M14A M14D MS-001 N14A
Contextual Info: Revised July 1999 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output

74LS132

Abstract: SN74LS132 SN74LS132D SN74LS132N
Contextual Info: SN74LS132 Quad 2-Input Schmitt Trigger NAND Gate The SN74LS132 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have

DM74LS132

Abstract: DM74LS132M DM74LS132N J14A M14A N14A W14B DM54LS132J DM54LS132W
Contextual Info: DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs General Description This device contains four independent gates each of which performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a slowly

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00SJ LVX00 M14A M14D MTC14
Contextual Info: 74LVX00 Low Voltage Quad 2-Input NAND Gate Features General Description • Input voltage level translation from 5V to 3V The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

74ACTQ00

Abstract: 74ACTQ00PC 74ACTQ00SC M14A MS-001 N14A
Contextual Info: Revised December 1998 74ACTQ00 Quiet Series Quad 2-Input NAND Gate General Description Features The ACTQ00 contains four 2-input NAND gates and utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold

Contextual Info: Revised November 2004 74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs General Description Features The VCX132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function

54ACT00

Abstract: 54AC00 54ACT 74AC AC00
Contextual Info: 54AC00/54ACT00 Quad 2-Input NAND Gate General Description The ’AC/’ACT00 contains four 2-input NAND gates. Features n Standard Microcircuit Drawing SMD — ’AC00: 5962-87549 — ’ACT00: 5962-87699 n 54AC00 now qualified to 300Krad RHA designation,

74ALVC132

Abstract: 74ALVC132M 74ALVC132MTC ALVC132 M14A MTC14
Contextual Info: Revised February 2005 74ALVC132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs General Description Features The ALVC132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function

stm cl-50

Abstract: 74LCX38Mx 74LCX38 74LCX38M 74LCX38MTC 74LCX38MTCX 74LCX38SJ 74LCX38SJX
Contextual Info: 74LCX38 National Semiconductor PRELIMINARY 74LCX38 Low Voltage Quad 2-Input NAND Gate Open Drain with 5V Tolerant Inputs General Description The LCX38 contains four 2-input open drain NAND gates. The inputs tolerate voltages up to 7V allowing the interface

74VCX132

Abstract: 74VCX132BQX 74VCX132M 74VCX132MTC M14A MLP014A MTC14 VCX132
Contextual Info: Revised February 2005 74VCX132 Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs General Description Features The VCX132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function

74AS1000

Contextual Info: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.

74LVQ00

Abstract: 74LVQ00SC 74LVQ00SCX 74LVQ00SJ 74LVQ00SJX M14A M14D s070 DD0-2
Contextual Info: National Semiconductor 74LVQ00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVQOO contains four 2-input NAND gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00SJ LVX00 M14A M14D MTC14
Contextual Info: Revised March 1999 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. • Input voltage level translation from 5V to 3V

74LVX00

Abstract: 74LVX00M 74LVX00MTC 74LVX00MTCX 74LVX00MX 74LVX00SJ LVX00 M14A M14D MTC14
Contextual Info: Revised February 2005 74LVX00 Low Voltage Quad 2-Input NAND Gate General Description Features The LVX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. • Input voltage level translation from 5V to 3V

SN74LS132M

Contextual Info: SN74LS132 Quad 2−Input Schmitt Trigger NAND Gate The SN74LS132 contains four 2-Input NAND Gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have

74F132

Contextual Info: Slgnellcs Document No. 853-0342 ECNNo. 98710 Date of issue November 27,1990 Status Product Spécification FAST Products FAST 74F132 Schmitt Trigger Q u a d 2-Input NAND Schm itt Trigger DESCRIPTION The 74F132 contains four 2-input NAND gates which accept standard TTL input