FLTL1723 Search Results

H723

Contextual Info: SN74LVC112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289 - JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS S'übmicron Process Typical V q lp (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

TL1723

Abstract: hstnn 199S SN74LVT16835
Contextual Info: SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS S C B S 3 0 9 C - M ARCH 1994 - REVISED JULY 1995 DGG OR DL PACK AG E TOP VIEW State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation

Contextual Info: SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D - D2932, MARCH 1987 - REVISED OCTOBER 1993 Contains Eight D-Type Flip-Flops With Single-Rail Outputs D W O R N PA C K AG E T O P V IE W Clock Enable Latched to Avoid False Clocking CE [ 1 1Q [ 2

SN54ABT16543

Abstract: SN74ABT16543 ABT16543
Contextual Info: SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS087B - FEBRUARY 1991 - REVISED JULY 1994 Members of the Texas Instruments Widebus Family State-of-the-Art EPIC-llB™ BiCMOS Design Significantly Reduces Power Dissipation

74AS871

Contextual Info: TEXAS INSTR LOGIC NOTICE SEE ORDER OF DATA FOR ERRATA ESE D • fiU17S3 QOflBTEE 1 ■ T-Vg-0?-0? S N 5 4 A LS 8 70 , SN 5 4AS 8 70 , S N 5 4 A LS 8 71, SN 5 4 A S 8 71 S N 74 A LS 8 70 , S N 74 A S 8 70 , S N 7 4 A L S 8 7 1 , S N 74 A S 8 71 INFORMATION

SN74ABT7819

Contextual Info: SN74ABT7819 512x18x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY _ Member of the Texas Instruments Widebus Family Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks