FLIP FLOP T TOGGLE Search Results

TTL 74109

Abstract: 8530510 74109 PIN CONFIGURATION 74109
Contextual Info: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 0 9 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, S e t and R eset inputs; also com ­

74LS113

Abstract: C0056
Contextual Info: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro­ nous S e t Sq input, w hen LOW , forces

Contextual Info: gl M O T O R O L A M C74AC109 M C 74A C T109 Dual J K Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. T h ejtocking operation is independent of rise and fall

14013B

Contextual Info: H D 14013B Dual D -ty p e Flip Flop The HD14013B dual type D flip-flop has independent Data, D , Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip-flops for counter and toggle

Contextual Info: f Z T SGS-THOMSON Ä T# HCC/HCF4013B IM E[HÎ(3 ilLi(OTM D(3S DUAL ’D' - TYPE FLIP-FLOP . SET-RESET CAPABILITY . STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ’’HIGH” OR "LOW” • MEDIUM-SPEED OPERATION - 16MHz (typ.)

Contextual Info: *SYNERGY SY10EL51 SY100EL51 DIFFERENTIAL CLOCK D FLIP-FLOP SEMICONDUCTOR DESCRIPTION FEATURES • 475ps propagation delay T he SY10/100EL51 are differential clock D flip -flop s with reset. T hese devices are fun ction a lly sim ila r to the E151 devices, with higher perform ance capabilities. With

16PIN

Abstract: 74F112 SOL16 TC74ACT112
Contextual Info: INTEGRATED T O SH IB A DUAL J - K TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 7 4 A C T 1 1 2P/F/FN DATA SILICON MONOLITHIC FLIP FLOP WITH PRESET AND CLEAR The TC74ACT112 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer

74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Contextual Info: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,

T112

Abstract: T-112
Contextual Info: INTEGRATED T O SH IB A DUAL J - K TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 7 4 A C T 1 1 2P/F/FN DATA SILICON MONOLITHIC FLIP FLOP WITH PRESET AND CLEAR The TC74ACT112 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer

Contextual Info: Philips Semiconductors-Signetics Document No. 853-0340 ECN No. 96144 Date of issue March 28.1989 Status Product Specification FAST 74F114 Flip-Flop Dual J-K Negative Edge-Triggered Flip-Flop With Common Clock And Reset FAST Products TYPE t y p ic a l ím a x

16PIN

Abstract: 74F112 SOL16 TC74AC112
Contextual Info: INTEGRATED T O SH IB A TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 7 4 A C 1 1 2P/F/FN DATA SILICON MONOLITHIC DUAL J - K FLIP FLOP WITH PRESET AND CLEAR The TC74AC112 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer

Contextual Info: ASSESS? CD74HC109, CD74HCT109 Dual J - K Flip-Flop with S e t and Reset Positive-Edge Trigger March 1998 Features Description • Asynchronous Set and Reset The Harris CD74HC109 and CD74HCT109 are dual J-K flipflops with set and reset. The flip-flop changes state with the

SOL16-P

Abstract: 16PIN 74F109 SOL16 TC74AC109
Contextual Info: INTEGRATED T O SH IB A TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 7 4 A C 1 09P/F/FN DATA SILICON MONOLITHIC DUAL J - K FLIP FLOP WITH PRESET AND CLEAR The TC74AC109 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer

74LS245N

Abstract: Philips FA 145 74LS245 74F112 I74F112D I74F112N N74F112D N74F112N signetics marking
Contextual Info: Philips Semiconductors-Signetics Document No. 853-0338 ECN No. 98775 Date of issue February 9 ,1 990 Status Product Specification FAST 74F112 Flip-Flop Dual J-K Negative Edge-triggered Flip-Flop FAST Products TYPE FEATURE T Y P 'C A L ^ a x 15mA 100MHz N74F112

Contextual Info: * DIFFERENTIAL CLOCK D FLIP-FLOP SYNERGY S E M IC O N D U C TO R SY10EL51 SY100EL51 DESCRIPTION FEATURES • 475ps propagation delay T he SY10/100EL51 are diffe re n tia l clock D flip -flop s with reset. T hese devices are fu n ction a lly sim ila r to the

gu43

Abstract: tms 374 BU 2735 AS SCAN182374A SCAN182374ASSC
Contextual Info: 182374A N a t i o n a l S e m i c o n d u c t o r SCAN182374A Serially Controlled Access Network D Flip-Flop with 25ft Series Resistor Outputs General Description Features The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • 525ps propagation delay The S Y 10 /1 00EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flop when the clock is LO W and is tran sfe rre d to the slave and,

CD4013BMS

Abstract: IOH15
Contextual Info: CD4013BMS S E M I C O N D U C T O R CMOS Dual ‘D’-Type Flip-Flop November 1994 Features Pinout • High-Voltage Type 20V Rating • Set-Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely With Clock Level Either “High” Or “Low”

TG150-50

Contextual Info: HARRIS SEMICOND SECTOR M3G5271 Q05131â 37E D 3875081 G E SOLID STATE 0 1E 13584 0 •¡HAS D ' T - P é - 0 7 -ö 7 CD4027A Types CMOS Dual J-K Master-Slave Flip-Flop The RCA-CD4027A is a single monolithic chip integrated circuit containing tw o iden­ tical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions

Contextual Info: HARRIS S E M I C O N D U C T O R CD4013BMS CMOS Dual ‘D’-Type Flip-Flop December 1992 Pinout Features • High-Voltage Type 20V Rating Q1 • Set-Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely With Clock Level Either “High” Or “Low”

Contextual Info: M M O T O R O LA Military 10535 Dual J-K Master Slave Flip-Flop ELECTRICALLY TESTED PER: MIL-M-38510/06104 Th e 10535 is a dual m aster-slave dc coupled J- K flip-flop. Asynchronous Set (S ) and R eset (R ) are provided. Th e set and reset inputs override the clock.

CD4013B

Abstract: CD4027BMS IOH15
Contextual Info: CD4027BMS S E M I C O N D U C T O R CMOS Dual J-K Master-Slave Flip-Flop December 1992 Features Pinout • High Voltage Type 20V Rating CD4027BMS TOP VIEW • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low”

design of the IC CD4013

Abstract: cd40138 cd4013 diagram cd4013 CD4013 internal diagram CD4013 IC
Contextual Info: H A R R IS S E M I C O N D U C T O R CD4027BMS CMOS Dual J-K Master-Slave Flip-Flop December 1992 Features • Pinout CD4027BMS TOP VIEW High Voltage Type 20V Rating • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either "High” or "Low”

CD4013

Abstract: F3302 harris CD4013B
Contextual Info: f f l U U H A R R CD4027BMS I S S E M I C O N D U C T O R CMOS Dual J-K Master-Slave Flip-Flop Decem ber 1992 Pinout Features C04027BMS TOP VIEW • H ig h V o lta g e T y p e 20V R a tin g • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely