FIPS Search Results

L6590

Abstract: SO16W
Contextual Info: L6590  FULLY INTEGRATED POWER SUPPLY FIPS PRODUCT PREVIEW Features WIDE-RANGE MAINS OPERATION ”ON-CHIP” 700V BVDSS POWER MOS 65kHz INTERNAL OSCILLATOR 2.5V ±2% INTERNAL REFERENCE STANDBY MODE FOR HIGH EFFICIENCY AT LIGHT LOAD OVERCURRENT AND LATCHED OVERVOLTAGE PROTECTION

verilog code for 32 bit AES encryption

Abstract: FIPS-197 SP800-38A EP3C40-6
Contextual Info: AES-P Programmable AES Encrypt/Decrypt Megafunction Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) Single module efficiently integrates multiple AES functions and modes Run-time programmable for: − Encryption or Decryption − Cipher Key length:

SP800-38A

Abstract: FIPS-197 verilog code for 128 bit AES encryption verilog code for 32 bit AES encryption verilog code for AES algorithm verilog code for aes encryption
Contextual Info: Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) AES-C Single module efficiently integrates multiple AES functions AES Optimized Encrypt/Decrypt Core Run-time programmable for: The AES-C core implements hardware data encryption and decryption using Rijndael

verilog code for implementation of des

Abstract: 3S1200E-4 verilog code for des
Contextual Info: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.

verilog code for implementation of des

Abstract: verilog code for des tsmc sram des verilog RTL 604
Contextual Info: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.

667 ecb

Abstract: verilog code for implementation of des verilog code for des tsmc sram
Contextual Info: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Core Verilog IP Core The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.

Contextual Info: Abridged Data Sheet DS28CN01 1Kbit I²C/SMBus EEPROM with SHA-1 Engine www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications FIPS 180-1/180-2 and ISO/IEC 101183 Secure Hash Algorithm (SHA-1). The memory is

SO16 wide package

Abstract: Optcoupler L6590 SO16W
Contextual Info: L6590 FULLY INTEGRATED POWER SUPPLY FIPS PRODUCT PREVIEW Features WIDE-RANGE MAINS OPERATION "ON-CHIP" 700V BVDSS POWER MOS 100kHz INTERNAL OSCILLATOR 2.5V ±2% INTERNAL REFERENCE STANDBY MODE FOR HIGH EFFICIENCY AT LIGHT LOAD OVERCURRENT AND LATCHED OVERVOLTAGE PROTECTION

Contextual Info: ABRIDGED DATA SHEET DS28E15 1-Wire SHA-256 Secure Authenticator with 512-Bit User EEPROM General Description Features The DS28E15 combines crypto-strong bidirectional secure challenge-and-response authentication functionality with an implementation based on the FIPS

DS28E02

Abstract: DS28E02P TSOC CRC16 CRC-16 T633 T633-2 21038
Contextual Info: ABRIDGED DATA SHEET Rev 0: 6/10 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm SHA-1 . The 1024-bit EEPROM array is configured as

TSOC 6

Abstract: 28E22
Contextual Info: ABRIDGED DATA SHEET EVALUATION KIT AVAILABLE DS28E22 DeepCover Secure Authenticator with 1-Wire SHA-256 and 2Kb User EEPROM General Description The DS28E22 combines crypto-strong, bidirectional, secure challenge-and-response authentication functionality with an implementation based on the FIPS

Contextual Info: Government Security Products G83-6744 Smart Card Keyboards Full QWERTY Keyboard with Integrated FIPS 201 Certified Smart Card Reader Cable Length: • Approx. 1.75 m  Approx. 5.74 ft. Actual product may vary from picture shown USB keyboard with chipcard reader

Contextual Info: ABRIDGED DATA SHEET 219-0008; Rev 1; 3/12 1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm SHA-1 . The 1024-bit EEPROM array is configured as

STM1404

Contextual Info: STM1403 3 V FIPS-140 security supervisor with battery switchover Features • ■ STM1403 supports FIPS-140 security level 3+ – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm SAL on tamper detection

BAT54J

Abstract: FIPS-140 STM1403 STM1404
Contextual Info: STM1403 3 V FIPS-140 security supervisor with battery switchover Features • STM1403 supports FIPS-140 security level 3+ – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm SAL on tamper detection

DP4201J

Contextual Info: Microprocessor Support Circuits DP4201 National Semiconductor DP4201 Clock Generator General Description Features The DP4201 C lo ck G enerator is designed fo r 4 00 4 m ic ro -c o m p u te r series fa m ily a p p lica tio n s, and satisfies c lo c k signal requ ire m e n ts M C S - 4 0 " ^ and FIPS 4 -B it

STM1404

Abstract: 1N5817 BAT54J FIPS-140 STM1404A STM1404B STM1404C
Contextual Info: STM1404 3 V FIPS-140 security supervisor with battery switchover Features • ■ ■ ■ STM1404 supports FIPS-140 security level 4 – Four high-impedance physical tamper inputs – Over/under operating voltage detector – Security alarm SAL on tamper detection

Contextual Info: Atmel ATECC108 Atmel CryptoAuthentication SUMMARY DATASHEET Features   Secure authentication and product validation device High-Speed Public Key Algorithm PKI Crypto Engine ○ FIPS186-3 Elliptic Curve Digital Signature Algorithm (ECDSA)   

STM7007

Contextual Info: STM7007 Single-chip hardware accelerated encryption engine for computer and peripherals applications Data brief Features • World class encryption engine – HardCache Crypto module – FIPS 140-2 security level 3 – NIST Certificate #1599 ■ Symmetric algorithms NIST FIPS approved

DS28CN01

Contextual Info: Abridged Data Sheet DS28CN01 1Kbit I²C/SMBus EEPROM with SHA-1 Engine www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications FIPS 180-1/180-2 and ISO/IEC 101183 Secure Hash Algorithm (SHA-1). The memory is

cbc 327

Abstract: verilog code for 128 bit AES encryption FIPS-197 SP800-38A EP3SE50 verilog code for 32 bit AES encryption verilog code for AES algorithm
Contextual Info: Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) AES-C Single module efficiently integrates multiple AES functions AES Optimized Encrypt/Decrypt Megafunction Run-time programmable for: The AES-C megafunction implements hardware data encryption and decryption using

verilog code for implementation of des

Abstract: Data Encryption Standard DES
Contextual Info: FIPS 46-3 Standard Compliant Encryption/Decryption performed in 48 cycles ECB mode DES3 Up to 168 bits of security Triple Data Encryption Standard Megafunction Verilog IP Megafunction The DES3 megafunction implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.

tamper detection sensors

Abstract: STM1404 BLD 122 BLD-3 1N5817 BAT54J FIPS-140 STM1404A STM1404B STM1404C
Contextual Info: STM1404 3V FIPS-140 Security supervisor with battery switchover Features • ■ ■ ■ STM1404 supports FIPS-140 security level 4 – Four high-impedance physical tamper inputs – Over/Under operating voltage detector – Security alarm SAL on tamper detection

3S500E-5

Abstract: sha1 verilog code for sha1 hash function
Contextual Info:  Compliant to the FIPS 180-1 specification for SHA-1.  Bit padding. SHA1 SHA-1 Secure Hash Function Core  264-1 bits maximum message length.  Supported Message lengths mul- tiple of 8-bits.  Initial values of Chaining Va- riables selected before