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Faraday Electronics Inc FE3031-JK ELECTRONIC COMPONENT
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components ()	FE3031-JK		160			1 $587.74 10 $503.78 100 $503.78 1000 $503.78 10000 $503.78	Buy Now
	FE3031-JK		104			1 - 10 - 100 - 1000 - 10000 -	Buy Now
Western Digital Corp FE3031A-JK INTERFACE CIRCUIT, CMOS, PQCC100
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components ()	FE3031A-JK		124			1 $500.26 10 $428.80 100 $428.80 1000 $428.80 10000 $428.80	Buy Now
	FE3031A-JK		10			1 - 10 - 100 - 1000 - 10000 -	Buy Now
Western Digital Corp FE3031-JK ELECTRONIC COMPONENT
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Quest Components	FE3031-JK		10			1 $587.74 10 $503.78 100 $503.78 1000 $503.78 10000 $503.78	Buy Now
Honeywell Sensing and Control / MICRO SWITCH FE-30310 Basic / Snap Action Switches V BASIC SW
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Sager	FE-30310					1 - 10 - 100 - 1000 - 10000 -	Buy Now
Honeywell Sensing and Control / MICRO SWITCH FE-30314 Basic / Snap Action Switches Sealed SE Switch
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Sager	FE-30314					1 - 10 - 100 - 1000 - 10000 -	Buy Now

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FE3031 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
fe3031 Abstract: 74lsxxx 80286 DMA ic 80286 Contextual Info: FE3031 INTRODUCTION 1.0 INTRODUCTION 1.1 DESCRIPTION 1.2 The FE3031 is an IBM* AT data buffer and parity generator/checker in a 100-pin PLCC package that contains all of the data buffers necessary to im plem ent an AT com patible computer. The FE3031 functions as a peripheral data bus buffer,	OCR Scan	fe3031 100-pin fe3600b 16-bit +374lsxxx 80286 dma ic 80286	PDF
FE3010 Abstract: FE3001 Contextual Info: FE3031A INTRODUCTION 1.0 INTRODUCTION 1.2 1.1 DESCRIPTION The FE3031A is an IBM AT data buffer and parity generator/checker in a 100-pin PLCC package that contains all of the data buffers necessary to implement an AT compatible computer. The FE3031A functions as a peripheral data bus buff	OCR Scan	fe3031a 80386sx fe3600 100-pin +3onbrd16 fe3010 fe3001	PDF
80288 Contextual Info: FE3031 WESTERN DIGITAL DATA 0:7 D ( 0:7 ) 646 í É EDATA ( 0:7 ) D ( 8:15 ) DATA (8:15) MDATA ( 0:7 ) 646 PARITY OUTPUTS PARITY INPUTS 280 646 PARITY ERROR MDATA (8:15) MEMR YMEMÏT 245 YMËMW Figure 2. FE3031 Functional Block Diagram AT Data Buffer I	OCR Scan	fe3031 0ata15 0ata13 data11 +5data10 mdata15 mdata14 mdata13 80288	PDF
FE3020 Abstract: FE3030 Western Digital microprocessor 80286 Word Size FE3010 FE3001A FE3031 8254 cascading FE3000A 80386SX Contextual Info: WESTERN DIGIT AL CORP SIE D • T?iaEEÔ OQOSÔS4 O l - S Z '3 3 - ìS ■ Advance Information FE3010B AT Peripheral Control Device □ □ □ □ □ 100% hardware and software compatible to the IBM* AT* 15 interrupt channels 3 timer channels 7 DMA channels	OCR Scan	fe3010b fe3400b fe3600b 80386sx +12fe3017 t-52-33-15 fe3010 84-pln fe3020 fe3030 western digital microprocessor 80286 word size fe3001a fe3031 8254 cascading fe3000a	PDF
fe3021 Abstract: 64K DRAM 80286 schematic 80286 mouse D4000-D7FFF 0F80000FFFFF 8042 keyboard controller LIM EMS 4.0 FE3010B Contextual Info: WESTERN DIGITAL CORP “'" system s lòg' i c / 4DE D • T71fl22ä aG0bSS3 Q Hlii»C péripheral t - 5 2 ,- 3 3 - 2 - 1 FE3021 Address Bujfer and Memory Controller f SS WESTERN DIGITAL WESTERN D IG IT A L CORP 40E D ■ 1716223 OOQbSSM 2 H l i l DC FE3021	OCR Scan	t71fl22 fe3021 t-52-33-21 nii104 +864k dram 80286 schematic 80286 mouse d4000-d7fff 0f80000fffff 8042 keyboard controller lim ems 4.0 fe3010b	PDF
fe3031 Abstract: FE3010C Contextual Info: FE3010C INTRO DUCTIO N 1.0 INTRODUCTION 1.1 DESCRIPTION As part of the Western Digital FE3600B and FE3600C chip sets, the FE3010C AT Peripheral Control Device allows designers to build PC/AT Bus compatible single board computers that will operate at speeds from 10 MHz to 20 MHz with	OCR Scan	fe3010c fe3600b fe3600c 80386sx +3fe3001 fe3021 fe3031	PDF
FE3031 Abstract: 8254 TIMER timer 8254 circuit FE3001 FE3010C FE300 80286 interrupt table intel 8259 interrupt controller command word of 8259 Contextual Info: FE3010C INTRO DUCTIO N 1.0 INTRODUCTION 1.1 DESCRIPTION 8259 interrupt controllers in cascade mode. Addi tional features include 15 interrupt channels, 3 timer channels, 7 DMA channels, DMA page registers, 8 MHz DMA, and TTL compatibility. As part of the Western Digital FE3600B and	OCR Scan	fe3010c fe3600b fe3600c 80386sx +10fe3001 fe3021 fe3031 80386sx-based 8254 timer timer 8254 circuit fe300 80286 interrupt table intel 8259 interrupt controller command word of 8259	PDF
fe3001 Contextual Info: FE3001 WESTERN DIGITAL Figure 2. FE300I Block Diagram AT Control Logic I FE3001 WESTERN DIGITAL 84 1 CLK16 CLKHS 83 CLK14 55 56 RESIN PROCLK SYSCLK DMACLK TMRCLK PCLK PCLK ftÉSÓPU CLK287 ÒLYWR DMAMR RESET ÖNBRDL" 50 CPURES 51 MNIO MÉMC316 IOCS 16 ¿EROWS	OCR Scan	fe3001 fe300i clk14 clk16 +2clk287 mc316	PDF
80286 schematic Abstract: lp9 pinout fe3031 FE3021A 8042 "Keyboard Controller" A1981 8042 keyboard controller LIM EMS 4.0 tl982 c3fff Contextual Info: FE3021 DESCRIPTION 1.0 DESCRIPTION 1.1 The FE3021 is a 16 MHz AT address buffer and memory controller in a 132-pin JEDEC package. Chip count is significantly reduced by integrating the memory controller, AT bus address buffers, and I/O into one chip. The memory controller is a	OCR Scan	fe3021 132-pin fe3600b as5s23s36s3 +120io10 tl982 132posn 80286 schematic lp9 pinout fe3031 fe3021a 8042 "keyboard controller a1981 8042 keyboard controller lim ems 4.0 c3fff	PDF
RL3 T125/55 Abstract: FE3010 FE3001A 80387SX Contextual Info: FE3001A INTRO DUCTIO N 1.0 INTRODUCTION 1.1 DESCRIPTION 1.2 The FE3001A contains all of the clock generation and cycle control logic necessary to implement an IBM AT compatible computer. It is part of the FE3600B/C chip set intended to simplify the design	OCR Scan	fe3001a fe3600b/c 80286/80386sx 84-pin +516-bit 8/16-bit rl3 t125/55 fe3010 80387sx	PDF
FE3020 Abstract: EE3030 intel 80286 block diagram FE3030 intel 80286 TECHNICAL fe3000 FE3010 Contextual Info: WESTERN DI GI T AL CO RP SIE D • T?läEEÖ OQOSÖS4 0 ■ T 5 Z -5 3 -IS • Advance Information FE3010B AT Peripheral Control Device □ □ □ □ □ 100% hardware and software compatible to the IBM* AT* 15 interrupt channels 3 timer channels 7 DMA channels	OCR Scan	fe3010b fe3400b fe3600b 80386sx +8t7lfl22fl fe3010 fe3020 ee3030 intel 80286 block diagram fe3030 intel 80286 technical fe3000	PDF
fe3031 Abstract: FE3010 80287 8042 keyboard controller LIM EMS 4.0 Contextual Info: FE3001 INTRODUCTION 1.0 INTRODUCTION 1.1 DESCRIPTION 1.2 The FE3001 contains all of the clock generation and cycle control logic necessary to implement an IBM AT compatible computer. It is pari of the FE3600 chip set intended to simplify the design of 80286 based AT computers.	OCR Scan	fe3001 84-pin fe3600 8/16-bit +616-bit fe3031 fe3010 80287 8042 keyboard controller lim ems 4.0	PDF
37C65 Abstract: c5287 FE3001 FE3031 T58-T57 D 80287-8 em-180 PFA 10Z FE3010B FE3021 Contextual Info: WESTERN DIGITAL CORP 4QE D m =1710220 Q0QbSS3 Q •■ bil>C fri . „ SYST EM S L Ö GIC / P ERIP H ERA L " ' I ^ T S 1 ^ 3 » '2 . \ FE3021 Address Buffer and Memory Controller •HÜWESTERN DIGITAL H Powered by ICminer.com Electronic-Library Service CopyRight 2003	OCR Scan	fe3021 t-52-33-21 171fleaa 37c65 +8c5287 fe3001 fe3031 t58-t57 d 80287-8 em-180 pfa 10z fe3010b	PDF
80286 schematic Abstract: fe3031 80286 mouse Western Digital floppy disk FE3021A FE3001a FE3031A CHIPset for 80286 8042 keyboard controller floppy controller Contextual Info: V m =1710226 O O G b b ll T • UDC " T '5 2 - 3 V 2 . 1 FE3021A Address Buffer and Memory Controller g? WESTERN DIGITAL WESTERN D IG IT A L CORP HOE D H =1716523 aO O bblE 1 HUDC FE3021A TABLE OF C O N TEN TS T-52-33-21 Page P R E F A C E .	OCR Scan	fe3021a t-52-33-21 j71fl22fl 132-pin +980286 schematic fe3031 80286 mouse western digital floppy disk fe3001a fe3031a chipset for 80286 8042 keyboard controller floppy controller	PDF