F101 Search Results

application of parity checker/generator

Abstract: PQO-10 F10170 F10570
Contextual Info: F1017Ö« F10570 11-INPUT PARITY CHECKER/GENERATOR D E S C R IP T IO N — T h e F 1 0 1 70 a n d F1 0 5 70 a re v e ry h ig h -s p e e d 1 1 -In p u t P a rity C h e c k ­ e r /G e n e ra to rs . It is u s e fu l f o r d a ta p ro c e s s in g , m e m o ry a n d d a ta tr a n s m is s io n a p p lic a ­

F10166

Abstract: F10566
Contextual Info: F10166^ F10566 5-BIT COMPARATOR F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10166/F10566 are high-speed expandable 5-Bit Comparators for comparing the magnitude of two binary words. Two outputs are provided: A>B and A<B. A = B can be obtained by NORing the two outputs with an additional gate. A HIGH level on the

F10132

Abstract: F10532
Contextual Info: F10132 • F10532 DUAL MULTIPLEXER/LATCH h QnnaratoT h F1° 132 and F10532 are dual m ultiplexers w ith D type latches !? S° lect and Reset i nP“ ts. Each latch may be enabled “ LOGIC SYMBOL In a b « f p 'u n n i fl*K ^ 0n Enable <Ec) in ,he LOW sta,e or bV using the

F10186

Abstract: F10586 low power T Flip-Flop
Contextual Info: I HEX D FLIP-FLOP WITH RESET F10K VOLTAGE COMPENSATED ECL D E S C R I P T I O N — T h e F10186 and F10586 co n ta in six h ig h -sp e e d m aster/slave D -type flip -flo p s w h ich have a c o m m o n c lo c k . D ata is entered into th e m aster w hen th e C lo c k is

F10162

Abstract: F10562 decoder active high outputs
Contextual Info: F10162 • F10562 l-OF-8 DECODER ACTIVE HIGH OUTPUTS D E S C R IP TIO N — T h e F10162 a n d F10562 a c c e p t a 3 -b it b in a r y in p u t a n d p ro v id e s e ig h t m u tu a lly e x c lu s iv e o u tp u ts . T h e s e le c te d o u tp u t w ill be H IG H w h ile a ll o th e r

F10135

Abstract: F10535 fairchild ECL
Contextual Info: F10135~* F 1 0 5 3 5 ^ F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled Flip­ Flop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

F10141

Abstract: F10541
Contextual Info: F10141 • F10541 UNIVERSAL SHIFT REGISTER F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F1Q141/F10541 contains four clocked D type flip-flops with individual inputs and outputs for parallel operations, and with serial inputs and steering logic for bidirectional shifting. T he flip-flops accept input data a set-up tim e before the positive-going

WR112 5W Load

Contextual Info: P B tiG E C p l e s s e y DS3536-1.1 F1013-49 & F1147/48 LOW POWER WAVEGUIDE CIRCULATORS * FREQUENCY COVERAGE 7.75 - 40.0GHz * CIRCULATORS AND ISO-CIRCULATORS AV A ILA B LE * 4-PORT VERSIONS IN R120 & R140 * COMPACT AND ROBUST CONSTRUCTION This data sheet describes a standard range of 3-port circulators and iso-circulators in R84, R100,

Contextual Info: EDD H br D15D20 TITLE F E D C B A REV 11/10/11 1/14/08 1/14/08 10/30/07 10/09/07 2/28/07 02/17/04 DATE SP MCS MCS MCS MCS AWM ALM BY REVISION 11-1238 08/F0015 NO CHANGE 07-F1088 07-F1013 07-F0187 07-F0187 EN NUMBER INC. INC. 8851 SW OLD KANSAS AVE STUART, FL 34997

VTXO4310H-60.000MHZ

Contextual Info: • M F1018S-1 FOR DIGITAL MOBILE TELEPHONE, Tx DESCRIPTION FEATURES This SAW filter for the transmitting RF circuit of dig ita l m ob ile c o m m u n ica tio n e q u ip m e n t operating at 940 MHz ~ 960 MHz. 1. SMD package insures small size, lightweight.

bcd counter using j-k flip flop diagram

Abstract: pn sequence generator using jk flip flop F10136 ECL Handbook
Contextual Info: / / / F10136 • F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/FI 0537 are 4-stage synchronous counters capable of operating at typical count rates of 250 MHz. The circuits are designed

Contextual Info: F10176^ F10576^ HIGH SPEED HEX D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL D E S C R IP TIO N — The F10176 and F10576 contain six high-speed master/slave D type flip-flops which have a common Clock. Data is entered into the master when the Clock is LOW. Data transfer takes place on the positive-going clock transition. A change in the

8 bit adder and subtractor

Abstract: F10580 ECL ADDER adder H1211 F10180
Contextual Info: ; F10180 • F10580 / F10K VOLTAGE COMPENSATED ECL DUAL 2-BIT ADDER/SUBTRACTOR DESCRIPTION - The F10180/F10580 are high-speed, low-power Dual 2-Bit Adder/ Subtractors. It is designed to be used in special purpose adder/subtractors or in high speed multiplier arrays. Inputs for each adder are Carry-in, Operand A, and Operand B;

12J2

Abstract: 1.2j2 F10535 F10135
Contextual Info: F10135^ F10535 F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled FlipFlop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

Contextual Info: F1017Ó7* F10570 11-INPUT PARITY CHECKER/GENERATOR D E S C R IP TIO N — The F10170 and F10570 are very high-speed 11-In p u t Parity C heck­ er/G ene rato rs. It is useful fo r data processing, m e m ory and data tra nsm ission a p p lic a ­ tio n s. T w o o u tp u ts are provided; PoO-8 is H IG H w hen the re is an odd n u m b e ro f H IG H

F10116

Contextual Info: F10115 • F10116 • F10515 • F10516 LINE RECEIVERS DESCRIPTION — The F10115 and F10116 are d iffe re n tia l am p lifiers w ith low im­ pedance em itter-follow er outputs. An internal reference supply V b b is available for added ve rsatility. Active current sources provide im proved comm on mode rejection.

Contextual Info: Order this data sheet MOTOROLA by M R F10120H/D SEMICONDUCTOR TECHNICAL DATA F10120H* MHz Microwave Power Transistor 120 Watts NPN 960-1215 MHz .ill! CPT0 Designed for long pulsed common base amplifiers. Guaranteed Performance at 1215 MHz - Output Power = 120 Watts Peak

Contextual Info: F10153 • F10553 FIOK VOLTAGE COMPENSATED ECL QUAD D LATCH DESCRIPTION - The F10153/F10553 are high-speed Quad D Latches consisting of four bistable latch circuits with D type inputs and gated Q outputs. The gated outputs allow direct wiring to a bus. When the enable is LOW, outputs will follow the D inputs.

7473 JK flip flop

Abstract: IC 74LS73 74LS73D 7473PC 74LS73 dual JK JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 74LS73 JK JK flip flop IC diagram
Contextual Info: 73 CO NNECTIO N DIAGRAM PINOUT A •A /Â 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP With Separate Clears and Clocks) D E S C R IP TIO N — The ’73 and ’H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled

Contextual Info: Tape & Reel Packaging TR-F101 Tape Width, mm 8 Device Cavity Pitch, mm 4 Reel Size, inches 7 Devices per Reel 10, 50, 100, 200, 500, 1000, 2000 Mini-Circuits carrier tape materials provide protection from ESD Electro-Static Discharge during handling and transportation. Tapes are static dissipative and comply with industry standards EIA-481/EIA-541.

Contextual Info: POLYFET R F DEVICES SbE D • 724100^ 0000052 fl ■ 7\39’09 POLYFET RF DEVICES F1013 PATENTED GOLD METALIZED SILICON RF POWER MOSFET General Description Silicon vertical DMOS designed specifically for RF applications. Immune to forward and reverse bias secondary breakdown.

Contextual Info: Request a Quote | Ask an Engineer Image description. Print this Sheet End of image description. Image description. as PDF EndSave of image description. SMF635-F1010 10.95 GHz to 12.75 GHz Communications PAC ISOLATORS & CIRCULATORS Specifications RF Frequency

HW1M-LF2020-20

Abstract: Circuit Diagrams HW1M-LF1111-22N9 HW1M-F0101-20 HW-F10 HW IDEC hwf10 HW1M-F0202-40
Contextual Info: Oiltight Switches and Pilot Devices HW Series: 22mm Mono Lever Switches Assembled Part Numbers: Mono Lever Switches No. of Description Part Number Positions A HW1M-F1010-20 HW1M-F2020-20 HW1M-F0202-20 HW1M Standard Lever HW1M-F0101-40 Part Number Guide ➁

Contextual Info: F10135 • F10535 F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled FlipFlop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of