F TTL FAMILY CHARACTERISTICS Search Results

idt54

Abstract: S101-05 S10-171 74FCT821CT
Contextual Info: i f dt) IntegratedDeviceTechnotosyInc ADVANCE INFORMATION FCTXXXCT TTL OUTPUT ONLY SERIES HIGH-SPEED CMOS LOGIC FEATURES: DESCRIPTION: • FCTXXXCT series 25% faster than FCTAT speeds • CMOS devices with TRUE TTL input and output com patibility The FCTXXXCT is a high-speed CMOS logic family designed

Contextual Info: SC1302A/B/C/D/E/F Dual High Speed Low-Side MOSFET Driver POWER MANAGEMENT Features Description „ The SC1302A/B/C/D/E/F family are low cost dual low-side MOSFET drivers. These drivers accept TTL-compatible inputs and are capable of supplying high current outputs

SC1302A

Abstract: SC1302B SC1302C
Contextual Info: SC1302A/B/C/D/E/F Dual High Speed Low-Side MOSFET Driver POWER MANAGEMENT Features Description „ The SC1302A/B/C/D/E/F family are low cost dual low-side MOSFET drivers. These drivers accept TTL-compatible inputs and are capable of supplying high current outputs

TL390

Contextual Info: COM’L: -5/7/B/B-2/A, 10/2 F IN A L PAL20R8 Family AdvaH niccero 24-Pin TTL Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • 5-ns propagation delay ■ Power-up reset for initialization ■ Popular 24-pin architectures: 20L8, 20R8, 20R6, 20R4

PAL20LB

Abstract: mmi 20L8 amd part marking 20L8 PAL20L8 PAL20R4 PAL20R6 PAL20R8 PAL20L8-7
Contextual Info: F IN A L C O M 'L : -5 /7 /B /B -2 /A , 10/2 a Advanced Micro Devices PAL20R8 Family 24-Pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS • 5*ns propagation delay ■ Power-up reset for Initialization ■ Popular 24-pin architectures: 20L8,20R8,

PAL16R8 MMI

Abstract: PAL16l8 MMI
Contextual Info: F 1N A L COM’L: -4/5/7/B/B-2/A, D/2 PAL16R8 Family AdvarS! 20-Pin TTL Programmable Array Logic Devices DISTINCTIVE CHARACTERISTICS • As fast as 4.5 ns maximum propagation delay ■ Power-up reset for initialization ■ Popular 20-pin architectures: 16L8,16R 8,16R6,

Contextual Info: PALI 6R8 Family F eatures/B enefits 16L8,16R8 16R6,16R4 Ordering Inform ation — Newer Products • Standard 20-pln architectures PALC16R8Q-25 C Q STD • TTL and CMOS versions • High speed, as test as 10 ns tPD for PAL16R8D Series PROGRAMMABLE ARRAY LOGIC

Contextual Info: V54FCT823A V74FCT823A 9-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS FCT FAMILY DATA SHEETS F EATU R ES •Direct CMOS Replacement for 29823 •Speed Equivalent to 29823 •Output Drive Equivalent to 29823 •CMOS Low Power 5nW typ. static •Outputs Compatible with both CMOS and TTL

1N3064

Abstract: 1N916 TE1000 TE3000
Contextual Info: DATA SHEET Bipolar Gate Arrays TE1000 Series Gate Array DESCRIPTION The TE1000 high-speed gate array is a member o f the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 1000 internal gates and has a total of 96 inputs,

dg303a

Abstract: DG300ABK DG303ABK
Contextual Info: DG300A, DG301A, DG303A June 1999 D ata S h eet F ile N u m b er TTL-Compatible, CMOS Analog Switches Features The DG300A through DG303A family of monolithic CMOS switches are truly compatible second source of the original manufacturer. The switches are latch-proof and are

Contextual Info: ACT 2 Family FPGAs F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed

EP330-12CN

Abstract: EP330 EP330-15CN EP330-15C EP330-15 EP330-15CFN
Contextual Info: C D f« C C D IC C HIGH-PERFORMANCE 8-MACROCELL ONE-TIME PROGRAMMABLE LOGIC DEVICES _ SRES002A - D3374, OCTOBER 1 9 8 9 - REVISED SEPTEMBER 1992 N PACKAGE Programmable Replacement for Conventional TTL, 74HC, and 20-Pin PLD Family TOP VIEW) High-Voltage EPIC Process Allows for

Contextual Info: DATA SHEET ÌÀTCT Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,

1N3064

Abstract: 1N916 TE1000 TE3000
Contextual Info: DATA SHEET ÌAT&T Bipolar Gate Arrays TE3000 Series Gate Array DESCRIPTION CAD FEATURES The TE3000 high-speed gate array is a member of the Customized TTL-ECL Gate Array family, designed using advanced oxil-isolated OXIL bipolar technology. It features 3000 internal gates and has a total o f 168 inputs,

Monolithic Memories PAL20L8

Contextual Info: ADV MICRO PLA/PLE/ARRAYS 1 t D È I üaS?S 5t DD571S0 T-46-13-47 20L8, 20R8 20R6, 20R4 PAL20R8 Family F eatures/B enefits Perform ance • Standard 24-pln architectures Several speed/power versions are available. • TTL and CMOS versions • High speed, as fast as 15 ns tPD for PAL20R8B Series

DS9471-R2

Abstract: MC68B00L M6800 programming manual sem 5025 MC6800P motorola M6800 MC6800 MC6800L MC6800 manual 9c4h
Contextual Info: ! M M O T O R O L A SEM IC O N DU C TO R S b _ . J E ~ I f c i \ BL ."J 8 AUST N TEXA 7 c ,'. MOS -B IT MICROPROCESSING U N IT M PU The MC6800 is a monolithic 8 -bit microprocessor forming the central control function for Motorola's M6800 family. Compatible with TTL, the

sx08a

Contextual Info: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades

A54SX16A

Contextual Info: v4.0  SX-A Family FPGAs u e Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5V PCI, 5V TTL, 3.3V LVTTL, 2.5V LVCMOS2 • 2.5V, 3.3V, and 5V Mixed-Voltage Operation with 5V Input Tolerance and 5V Drive Strength • Devices Support Multiple Temperature Grades

A54SX16A

Abstract: A54SX08 A54SX08A A54SX16 A54SX32 A54SX32A A54SX72A PAR64 REQ64 antifuse programming technology
Contextual Info: Preliminary v1.2 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

A54SX08

Abstract: A54SX08A A54SX16 A54SX16A A54SX32 A54SX32A A54SX72A PAR64
Contextual Info: v3.0 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

SX-APQ208

Abstract: A54SX16A
Contextual Info: v2.0 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

SX-APQ208

Abstract: A54SX16A
Contextual Info: v2.0.1 SX-A Family FPGAs Le a di n g- E d ge P er f o r m a n ce • Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and 2.5 V/3.3V LVTTL • 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength • Configurable Weak-Resistor Pull-up or Pull-down for

ecl 10K

Abstract: MC10H125 ttl 081 335 16 pin ttl ECL-logic
Contextual Info: ECL 10KH High-Speed Emitter-Coupled Logic Family M C 10H125 Quad ECL-to-TTL. Translator F eatu res/ Benefits PRELIMINARY INFORMATION T h is d o c u m e n t c o n ta in s spe* c if ic a t io n s and in fo r m a tio n w h ic h are s u b je c t to change. Ordering Inform ation

74xx151

Abstract: 74XX08 TTL 74XX04 74XX00 74xx161 74XX139 74xx04 TTL 74XX00 74XX174 74XX374
Contextual Info: National Semiconductor Application Note 319 Larry Wakeman June 1983 The MM54HC MM74HC family of high speed logic components provides a combination of speed and power characteristics that is not duplicated by bipolar logic families or any other CMOS family This CMOS family has operating