EPLD 900 Search Results

EPM7256

Contextual Info: EPM7256 EPLD High-Performance 256-Macrocell Device Data Sheet September 1992, ver. 2 □ Features. High-density, erasable CMOS EPLD based on second-generation Multiple Array Matrix MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 20 ns

EPM7128

Contextual Info: EPM7128 EPLD High-Performance 128-Macrocell Device Data Sheet December 1992, ver. 1 Features Preliminary Information □ □ □ □ □ □ □ □ High-density CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture 2,500 usable gates

CY7C344

Abstract: JESD22-A112 9815 EME-6300 JESD22
Contextual Info: Cypress Semiconductor Technology Qualification Report QTP# 91216/93321/97239/98153 VERSION 1.0 March, 2000 MAX  EPLD, P20 Technology, Fab 2 CY7C344 32-Macrocell MAX EPLD MAX is a Registered Trademark of ALTERA Corporation CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

EPM7032

Contextual Info: EPM7032 EPLD M . 32-Macrocell Programmable Logic Device September 1993, ver. 3 Features Data Sheet □ □ □ □ □ □ □ □ High-performance, erasable CMOS EPLD based on second-generation MAX architecture 600 usable gates Combinatorial speeds with t PD = 7.5 ns

Contextual Info: EP910 EPLD Features □ □ □ □ □ General Description Altera's EP910 Erasable Programmable Logic Device EPLD can implement up to 900 equivalent gates of SSI and MSI logic. It is available in windowed ceramic or OTP plastic 40-pin DIP and 44-pin J-lead chip carrier packages.

Contextual Info: EPM7096 EPLD Ü^ R*A\ High-Performance 96-Macrocell Device Data Sheet September 1992, ver. 2 Features □ High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture 1,800 usable gates Combinatorial speeds w ith tPD = 15 ns

Contextual Info: EPM7192 EPLD Ä N b jf e & r High-Performance 192-Macrocell Device \ Data Sheet September 1992, ver. 2 □ Features High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture 3,750 usable gates Combinatorial speeds with tPD = 12 ns

Contextual Info: EPM 7032V EPLD 3.3-Volt 32-Macrocell Device Data Sheet Features. □ Preliminary Information □ □ □ □ □ □ □ □ 3.3-V version of the popular EPM7032 EPLD Combinatorial speeds with t PD = 15 ns Clock frequencies up to 71 MHz Innovative power-saving features

910-A01

Contextual Info: EP910A EPLD High-Performance 24-Macrocell Device March 1993, ver. 2 Data Sheet Supplement Features □ □ P relim inary Inform ation □ □ □ □ □ □ Highest-performance 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz

EPM7160 Transition

Abstract: EPM7160-3 EPM7160 PLMJ7160-84 single one jk flipflop EPM7160-1 EPM7160-2 E7041 5628E
Contextual Info: EPM7160 EPLD AN b rs rA \ High-Performance 160-Macrocell Device Data Sheet September 1992, ver. 2 Features □ Preliminary Information □ □ □ □ □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture

programming epm7032

Abstract: epm7032 EPM7032 Transition EPM7128 EPLD epm7032 plcc
Contextual Info: EPM7032 EPLD 32-Macrocell Programmable Logic Device September 1993, ver. 3 Features Data Sheet □ □ □ □ □ □ □ □ H igh-perform ance, erasable CMOS EPLD based on second-generation MAX architecture 600 usable gates C om binatorial speeds w ith tPD = 7.5 ns

EPM7032

Abstract: altera EPM7032
Contextual Info: EPM7032 EPLD High-Performance 32-Macrocell Device Data Sheet September 1992, ver. 2 □ □ □ □ □ □ □ □ □ □ High-performance, erasable CMOS EPLD based on second-generation M ultiple A rray MatriX MAX architecture Com binatorial speeds w ith t PD - 1 0 ns

mod 8 using jk flipflop

Abstract: EPM7096 EPM7096 QFP DATA PLMJ7096-68
Contextual Info: ALTERA S3E CORP D • GSTS37S GOOS bl T bTl « A L T EPM7096 EPLD High-Performance 96-Macrocell Device Data Sheet I September 1992, ver. 2 Features □ High-density, erasable CMOS EPLD based on second-generation M ultiple Array M atrix MAX architecture 1,800 usable gates

Contextual Info: EP610A EPLD AN b r ^ n ^ \ High-Performance 16-Macrocell Device March 1993, ver. 2 Data Sheet Supplement □ Features □ □ □ P re lim in a ry Inform ation □ □ □ □ □ □ Highest-performance 16-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns

EP910

Abstract: ep910-30
Contextual Info: EP910 EPLD Features □ □ □ □ □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30,35, and 40 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

ALTERA EP610

Abstract: MIL-STD-883-compliant
Contextual Info: EP610 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 35 ns Counter frequencies up to 28.5 MHz Pipelined data rates up to 37 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

EP910

Abstract: altera EP910
Contextual Info: EP910 EPLD Features • ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs

Altera EP1810

Abstract: MIL-STD-883-compliant
Contextual Info: EP1810 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 45 ns Counter frequencies up to 22.2 MHz Pipelined data rates up to 33.3 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

EP610

Abstract: MIL-STD-883-compliant TI EP610 EP610-15 PALCE610 altera ep610 ALTERA MAX 5000 programming EP610-20 EP610I
Contextual Info: EP610 EPLD Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

EP610

Abstract: ep600i EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I
Contextual Info: EP610 EPLD H igh-perform ance, 16-macrocell Classic EPLD Com binatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Program mable I /O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

ATIC 64 C1

Contextual Info: EPS464 EPLD □ High-performance, globally-routed, general-purpose EPLD Combinatorial speeds as fast as 20 ns Counter frequencies up to 67 MHz Pipelined data rates up to 71 MHz 64 enhanced m acrocells and 256 shared expander product terms "exp an d ers" ; ideal for custom w aveform generation and state

altera ep900i

Abstract: IC MSI ADDER
Contextual Info: EP910 EPLD Features High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD as low as 12 ns Counter frequencies of up to 76.9 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs EP910, EP910I, and EP900I devices that are pin-, function, and

Contextual Info: MAR 1 « »93 EPM7032V EPLD 3.3-Volt 32-Macrocell Device Data Sheet January 1993, ver. 1 Features. □ □ Preliminary Information □ □ □ □ □ □ □ □ 3.3-V version of the popular EPM7032 EPLD Combinatorial speeds with tPD = 15 ns Clock frequencies up to 71 MHz

ALTERA MAX 5000 programming

Abstract: EP910-t altera EP910 24-MACROCELL osbt
Contextual Info: EP910 EPLD • Features ■ ■ ■ ■ ■ High-performance, 24-macrocell Classic EPLD Com binatorial speeds with t PD as low as 12 ns - Counter frequencies of up to 100 MHz - Pipelined data rates of up to 100 MHz Program m able I/O architecture with up to 36 inputs or 24 outputs