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Contextual Info: SY89538L 3.3V Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for |
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SY89538L SY89538L 750MHz M9999-092905-A | |
Optical Encoder
Abstract: US Digital
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136th Optical Encoder US Digital | |
zo 107 triac
Abstract: SN7401 triac zo 107 SN75107 transistor 107A equivalent 1N916 SN55107 SN55107A SN75107A SN75107B
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SN55107A, SN75107A, SN75107B, SN75108A SLLS069D SN55107A zo 107 triac SN7401 triac zo 107 SN75107 transistor 107A equivalent 1N916 SN55107 SN55107A SN75107A SN75107B | |
1706sContextual Info: 19-1198; Rev 0; 4/97 k \T A l i l X I V M 1 - t o 3-Cel l , H i g h - C u r r e n t , L o w - N o i s e , S t e p - U p DC-DC C o n v e r t e r s w i t h L i n e a r R e g u l a t o r Features The MAX1705/MAX1706 are high-efficiency, low-noise, s te p -u p DC-DC co n ve rte rs w ith an a u xilia ry linearregulator output. These devices are intended for use in |
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MAX1705/MAX1706 MAX1705 MAX1706 705/MAX 1706s | |
Contextual Info: ESUM Two Encoder to One Encoder Adder/Subtractor Page 1 of 4 Description The ESUM combines the quadrature outputs of two encoders into a single quadrature output. The output quadrature may be selected to be either the sum or difference of the two quadrature inputs. The index from encoder 0 is simply |
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Contextual Info: AD2B SEI to RS-232 Adapter 9-pin Page 1 of 3 Description The AD2B adapter allows the RS-485-like signal of SEI devices to interface to a standard RS-232 port (9-pin DB), such as those in IBM compatible PCs. The SEI (Serial Encoder Interface) bus is a simple, quick and convenient network of SEI |
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RS-232 RS-485-like PS-12 USB-232 | |
Contextual Info: AD7 HD25A Breakout Box Page 1 of 2 Description Connect the HD25A to the AD7 to have easy access to both the SEI bus and the analog output. The AD7 has both a power jack for plugging in a US Digital PS-12 power supply, and screw terminals for connecting a customer supplied power |
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HD25A PS-12 16VDC) RJ-12 USB-232 | |
Contextual Info: SY89538L 3.3V Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for |
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SY89538L SY89538L 750MHz M9999-110905-C | |
Contextual Info: USB-232 USB to USD RS232 Adapter Page 1 of 4 Description The USB-232 is an interface module that allows a USB 1.1 or USB 2.0 port to talk to US Digital RS232 devices such as the X3 MEMS inclinometer. The USB232 interface is usually ordered with a US Digital device and comes with the |
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USB-232 RS232 USB-232 USB232 USB-232. | |
Contextual Info: EPOT Voltage-to-Quadrature or Voltage-to-Step/Direction Converter Voltage-to-Quadrature or Voltage-to-Step/Direction Converter, Page 1 of 6 Description The EPOT converts an analog voltage into digital encoder signals. The output signals may be configured to produce either an A/B quadrature output or |
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26C31) | |
Contextual Info: EDAC2 Encoder Digital to Analog Converter Page 1 of 5 Description The EDAC2 converts the A and B quadrature output of an incremental encoder into a voltage that is proportional to the encoder position. The output from the encoder causes an internal 12-bit counter to count up or down. The output of the |
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12-bit PS-12 | |
SY89537L
Abstract: SY89538L SY89538LHG SY89538LHGTR 2352G MICREL 7550
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SY89538L SY89538L 750MHz M9999-062706-D SY89537L SY89538LHG SY89538LHGTR 2352G MICREL 7550 | |
EDIVIDE
Abstract: encoder disk rotary encoder volume
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LTA 703 S
Abstract: 126330V MAX1703ESE
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300kHz) 200kHz 400kHz) MAX1703 LTA 703 S 126330V MAX1703ESE | |
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quadrature encoder 16 pin dip
Abstract: encoder
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whe1026 PS-12 quadrature encoder 16 pin dip encoder | |
Contextual Info: SEI-USB SEI to USB Adapter Page 1 of 5 Description The SEI-USB is an interface module that connects US Digital's SEI compatible devices to a standard USB 1.1 / 2.0 port. The SEI Serial Encoder Interface bus is a simple, quick and convenient network that connects up to 15 addressable SEI devices using a single 6-wire |
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RS-485-like USB-232 PS-12 | |
Contextual Info: 19-4759; R ev 1; 1/99 JVW YXAJVX 1- Cel l t o 3 - C e l l , H i g h - P o w e r 1A , L o w -Noise, S te p - U p DC-DC C o n v e r t e r s Features The MAX1700/MAX1701 are high-efficiency, low-noise, step-up DC-DC converters intended for use in batterypow ered w ireless a p p lica tio n s. They use a synchron o u s-re ctifie d p u ls e -w id th -m o d u la tio n (PWM) b oo st |
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800mA 300kHz MAX1701) MAX1700/MAX1701 28lAD | |
Contextual Info: SY89538L 3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for |
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SY89538L SY89538L 750MHz M9999-010808-E | |
RJ12 female connector
Abstract: RJ12 PINOUT HD25A RJ12 socket EDIVIDE
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HD25A PS-12 16VDC) RJ-12 USB-232 RJ12 female connector RJ12 PINOUT RJ12 socket EDIVIDE | |
Contextual Info: EDAC2 Encoder Digital to Analog Converter Page 1 of 5 Description The EDAC2 converts the A and B quadrature output of an incremental encoder into a voltage that is proportional to the encoder position. The output from the encoder causes an internal 12-bit counter to count up or down. The output of the |
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12-bit 962escription USB-232 PS-12 | |
26c32Contextual Info: EADAPT Encoder Signal Converter Page 1 of 4 Description The EADAPT is an inline encoder signal converter which allows the user to invert or not-invert any of the A,B and Index encoder signals. This can be used to invert the encoder's rotation sense. The input quadrature signals can be singleended or differential. Single-ended inputs can have amplitudes up to 30V. In |
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10-position 26c32 | |
Contextual Info: EQUAD Up/Down Clock to Quadrature Encoder Page 1 of 4 Description The EQUAD converts any clock source into optical encoder quadrature outputs. When up clock / down clock mode is selected via DIP SW1 up-clocks generate an A leads B quadrature sequence and down clocks generate a B leads A |
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Contextual Info: SY89538L 3.3V, Precision LVPECL and LVDS Programmable Multiple Output Bank Clock Synthesizer and Fanout Buffer with Zero Delay General Description The SY89538L integrated programmable clock synthesizer and fanout is part of a precision PLLbased clock generation family optimized for |
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SY89538L SY89538L 750MHz M9999-010808-E | |
SY89537L
Abstract: SY89538L
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SY89538L SY89538L 750MHz M9999-010808-E SY89537L |