ECL100K Search Results

Contextual Info: GEC PLESSEY 1 S E M I C O N D U C T O R~S~] PRELIMINARY INFORMATION SP2001 100MHz DIRECT DIGITAL FREQUENCY SYNTHESISER Supersedes January 1991 Edition The SP2001 Direct Frequency Synthesiser (DFS) is an ECL100K compatible 'numerically controlled oscillator' i.e. it

BPECLDL-4.5-0.2

Abstract: ECL100K
Contextual Info: ECL100K COMPATIBLE 8-BIT BINARY/ DECADE PROGRAMMABLE LOGIC DELAY LINE # ECL 1 00 K in p u t and o u tp u t levels # Delays stable and precise # 3 4-pin DIP package .3 7 5 high # A vaila ble in delays up to 1 3 2 n s # A vaila ble in Binary and Decade versions

Contextual Info: lowprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # E C L 1 0 0 K in p u t and o u tp u t levels # D ual units w ith separate trigger inputs and panying outputs C onditions" shown. Pulse w id th s stable and precise on both leading and trailing edge.

100K series ECL

Contextual Info: ECL DIGITAL DELAY LINES E10 SERIES - ECL10K INTERFACED E100 SERIES - ECL100K INTERFACED Industry’s widest selection! 5nS - 200nS 500nS avail. Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K

ECL100K

Abstract: digital frequency multiplier
Contextual Info: lowprofile ECL100K COMPATIBLE DIGITAL FREQUENCY MULTIPLIER MODULE The EC L-100K -D FM M is offered in twenty-six 261 standard # ECL 1 0 0 K input and o utput levels # O utput w avetrain synchronized clock frequencies from 50 to 250 Mhz. W hen tested under the

Contextual Info: 2.5Gb/s GaAs 1:16 Demultiplexer 1C FMM4007KC-1 FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

demultiplexer ic

Contextual Info: 2.5Gb/s GaAs 1:16 Demultiplexer IC FMM4007KC-1 FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

Contextual Info: ECL100K COMPATIBLE 8-BIT BINARY/ DECADE PROGRAMMABLE LOGIC DELAY LINE # ECL 100K input and output levels # Delays stable and precise The Logic Delay Lines are digitally programmable by the presence of either a " 1 " or a " 0 " at each of the programming #

Demultiplexer IC

Abstract: ECL100K FMM4007KC-1 1 into 16 demultiplexer circuit diagram CLK16N
Contextual Info: 2.5Gb/s GaAs 1:16 Demultiplexer IC FMM4007KC-1 FEATURES • • • • • High Speed Operation up to 2.5Gbps Low Power Dissipation: 1.4W Typ Single Power Supply: VEE = -5.2V High Speed Differential I/O: 2.5GHz clock inputs ECL100K Compatible Parallel data I/O: Single-Ended 155Mbps parallel

Contextual Info: ECL100K COMPATIBLE RAMMABLE DELAY LINE ECL 10OK input and output levels Delay programming is accomplished in two decades using standard BC D code 1-2-4-8 on eight programming lines. The 100 picosecond steps are controlled by inputs to terminals P1, P2, P3 and P4 with P1 being the least significant bit. The 1

022080

Abstract: DECLPGM-2-10 ECL100K
Contextual Info: ENGI N E E R E D COMPONENTS CO 7 3 »e J 33335ñ3 ODGOSSS 7 "F S H *! hwprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # # # # # # # ECL 100K input and output levels Dual units with separate trigger inputs and outputs Pulse widths stable and precise

Contextual Info: ECL100K COMPATIBLE 8-BIT BINARY/ DECADE PROGRAMMABLE LOGIC DELAY LINE EC L 100K input and output levels Delays stable and precise 34-pin DIP package .375 high Available in delays up to 132ns Available in Binary and Decade versions Step resolution from 0.1 to 0.5ns

Contextual Info: ENGI N E E R E D COMPONENTS CO 7 3 »e J 33335ñ3 ODGOSSS 7 "F S H *! hwprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # # # # # # # ECL 100K input and output levels Dual units with separate trigger inputs and outputs Pulse widths stable and precise

Contextual Info: verylewprofile ECL100K COMPATIBLE LOGIC DELAY MODULE # 100K E C L input and outputs Delays stable and precise 24-pin DIP package .300 high Available in delays from 9 to 80ns 1 2 .5 % taps—each isolated and with 70 ECL DC fan-out capacity Fast rise time on all outputs

ecl 806

Abstract: 100K-ECL-LDM-40 ky 202 h 100K-ECL-LDM-16 ECL100K
Contextual Info: wry lowprofile ECL100K COMPATIBLE LOGIC DELAY MODULE _ j # 1 0 0 K ECL in p u t and o u tp u ts # D elays sta b le and precise + 2 4 -p in DIP package .3 0 0 high # A v a ila b le in delays fro m 9 to 8 0 n s # 1 2 .5 % ta p s — each isola ted and w ith

Contextual Info: lowprofile ECL100K COMPATIBLE DUAL PULSE GENERATOR MODULE # # # # % # # ECL 100K input and output levels Dual units with separate trigger inputs and outputs Pulse widths stable and precise 12-pin DIP package .325 high Available in pulse widths from 2ns to 50ns

Contextual Info: lowprofile ECL100K COMPATIBLE LOGIC DELAY MODULE # ECL 100K input and outputs # Delays stable and precise # 24-pin DIP package .375 high w ith each m o d ule in c o rp o ra tin g taps at 1 2 .5 % increm ents o f to ta l # Available in delays from 16 to 80ns

marking Z

Abstract: Power Dynamics ECL100K ecl100
Contextual Info: DYNAMICS CORP OF AMERICA-, A4 — DISCRETE TCXO’s: ECL, and SINEWAVE D e | 3DEDD4fl DODDSES 84D 00 22 5 3 0 2 0 0 4 8 D Y N A M I C S C O R P OF AMER ICA , P • 7 Z S & -2 - 3 PACKAGE STYLE 4. + 1 2 V D C TTL ECL100K SINEW AVE R-H PART NUMBER 03-02114-XXX

B9236

Abstract: CY7B933 STK*403-130 CY7B923 ECL100K
Contextual Info: CY7B923 CY7B933 HOTLink Transmitter/Receiver Features • • • • • • • • • • • • • • • • • • twisted pair . Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also available for high speed applications 160-400 Mbits/second), as

ECL100K

Abstract: MOS57T-107GM E022A
Contextual Info: NEL NS GM E022A Preliminary Feb. 29, 2000 MOS57T-107GM 10.7 Gb/s PLLType 16:1 MUX Module MOS57T-107GM is a 16:1 multiplexer module which was designed for use in the transmitter of optical systems. It combines 16 parallel data input signals operating at 666.5 Mb/s into a 10.7 Gb/s serial output signal and generates two clock output signals at

as1213

Abstract: CX20201-3 CX20202-3 HI20201 HI20203 HI20203JCB TL431CP
Contextual Info: August 2000 T UC T DUC ROD TE PRO at P E r T TITU ente OL E OBS LE SU BS upport C om/tsc sil.c al S SIB POS Technic ww.inter A R w ur FO IL or act o cont -INTERS Ultra 8 1-88 HI20203 8-Bit, 160 MSPS, High-Speed D/A Converter Features Description • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz

PE-68508

Abstract: PE 68508 pt4172 characteristics of twisted pair cable XF3506SIP TA 2092 N ECL100K ML6672 ML6674
Contextual Info: July 1999 ML6674 ATM 155Mbps UTP Transceiver GENERAL DESCRIPTION FEATURES The ML6674 is a complete monolithic transceiver for 155Mbps NRZ encoded data transmission over category 5 unshielded twisted pair UTP and shielded twisted pair (STP) cables. The ML6674 is compliant with the ATM

Contextual Info: f PRELIMINARY CYPRESS C Y 7 C 92 4D X 200 MBaud HOTLink Transceiver Features Second generation HOTLink™ technology Fibre Channel and ESC O N com pliant 8B /10B encoder/decoder 10- or 12-bit pre-encoded data path raw m ode 8- o r 10-bit encoded data transport (using 8B/10B

Contextual Info: DAC-330 10-Bit, Multiplying D/A Converter FEATURES A.Gmd • • • • • • • Vtxas 0 10-Bit resolution 160 MHz conversion rate Multiplying — 14 MHz bandwidth ECL compatible Single -5V supply Low-power Low-glitch 0L Biasing Circuii APPLICATIONS