ECL VIDEO Search Results

Contextual Info: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

Contextual Info: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs

F100K ECL 300 series and design guide

Abstract: F100K ECL book F100K AN-780
Contextual Info: Fairchild Semiconductor Application Note May 1991 Revised February 2004 Operating ECL from a Single Positive Supply Introduction ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the

DP8481

Contextual Info: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

Contextual Info: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with

F100K ECL 300 series and design guide

Abstract: ESD diode ,F100K ECL book AN-780 F100K F100K ECL book
Contextual Info: Fairchild Semiconductor Application Note May 1991 Revised May 2000 Operating ECL from a Single Positive Supply INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

MPD1750-04

Abstract: SC9103-07 ttl ecl
Contextual Info: Monolithic Multi-Throw Driver Chips 03Alpha MPD1750-04 Features • 4 ns Video Switching Time ■ Low in Band Noise: -5 0 dBm at 1 GHz ■ True Differential Inputs ■ Compatible with TTL, ECL, and CMOS to 5.0V ■ Internal Referenced for TTL, ECL ■ Inverting, Non-Inverting

Contextual Info: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver

HEP89V

Abstract: hp89 SY10EP89V SY10EP89VKC SY10EP89VKCTR SY10EP89VKI SY10EP89VKITR SY10EP89VZC SY10EP89VZCTR SY10EP89VZI
Contextual Info: Micrel, Inc. ECL Pro SY10EP89V 5V/3.3V 3GHz COAXIAL CABLE DRIVER FEATURES ECL Pro™ SY10EP89V DESCRIPTION • ■ ■ ■ ■ 3.3V and 5V power supply options 3.0GHz typical toggle frequency 310ps typical propagation delay 1.6V 5V and 1.4V (3.3V) swing

Contextual Info: SN65LVEL11 www.ti.com. SLLS927 – DECEMBER 2008 3.3 V ECL 1:2 Fanout Buffer

Contextual Info: SN65LVEL11 www.ti.com. SLLS927 – DECEMBER 2008 3.3 V ECL 1:2 Fanout Buffer

MC100LVEL11

Abstract: SLLS927 SN65EL11 SN65LVEL11 SN65LVEL11D SN65LVEL11DGK SN65LVEL11DGKR SN65LVEL11DR
Contextual Info: SN65LVEL11 www.ti.com. SLLS927 – DECEMBER 2008 3.3 V ECL 1:2 Fanout Buffer

T0401-01

Abstract: T0402
Contextual Info: SN65EL11 www.ti.com. SLLS920 – DECEMBER 2008 5-V PECL/ECL 1:2 Fanout Buffer

EE-25 200 6 transformer

Contextual Info: SPT SIGNAL PROCESSING TECHNOLOGIES SPT5510 16-BIT, 200 MWPS ECL D/A CONVERTER PRELIMINARY INFORMATION FEATURES APPLICATIONS • • • • • • • • • • • 16-Bit, 200 MWPS Digital-to-Analog Converter ECL Compatibility Fast Settling Time: 25 ns to ±0.01%

MC100EL11

Abstract: MC10EL11 SN65EL11 SN65EL11D SN65EL11DGK
Contextual Info: SN65EL11 www.ti.com. SLLS920 – DECEMBER 2008 5-V PECL/ECL 1:2 Fanout Buffer

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs

ECLC

Contextual Info: SPT SIGNAL PROCESSING TECHNOLOGIES SPT5510 16-BIT, 200 MWPS ECL D/A CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • 16-Bit, 200 MWPS Digital-to-Analog Converter ECL Compatibility Fast Settling Time: 25 ns to ±0.01% Low Glitch Energy

Contextual Info: SN10KHT5574 OCTAL ECLĆTOĆTTL TRANSLATOR WITH DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS AND 3ĆSTATE OUTPUTS SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 • • • • • DW OR NT PACKAGE TOP VIEW 10KH Compatible ECL Clock and TTL Control Inputs 1Q 2Q

SN100KT5574

Abstract: SN100KT5574DW SN100KT5574NT
Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS009 – D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

Contextual Info: SN10KHT5574 OCTAL ECLĆTOĆTTL TRANSLATOR WITH DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS AND 3ĆSTATE OUTPUTS SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 • • • • • DW OR NT PACKAGE TOP VIEW 10KH Compatible ECL Clock and TTL Control Inputs 1Q 2Q

Contextual Info: SP T SIGNAL PROCESSING TECHNOLOGIES SPT5510 16-BIT, 200 MWPS ECL D/A CONVERTER PRELIMINARY INFORMATION FEATURES APPLICATIONS • • • • • • • • • • • 16-Bit, 200 MWPS Digital-to-Analog Converter ECL Compatibility Fast Settling Time: 25 ns to ±0.01%

Contextual Info: SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014A – APRIL 1990 – REVISED JANUARY 1999 D D D D D D D DW OR NT PACKAGE TOP VIEW 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs