ECL 10161 Search Results

Contextual Info: data m delay devices; inc. Digitally Programmable Delay Units SERIES: PDU-1016 (4-Bit ECL Interfaced Specifications: • ■ ■ ■ ■ Features: ■ ■ ■ ■ ■ ■ Input & output ECL buffered 4-BIT ECL programmable delay line Output same polarity of input

a2c33

Contextual Info: ECL ISOPLANAR MEMORY F10411 256x1—BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL GENERAL DESCRIPTION - The F10411 is a low voltage 256-bit Read/Write Ran­ dom Access Memory, organized 256 words by one bit. It has a 20 ns typical access time

F10410

Contextual Info: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D ESC R IPTIO N - The F10410 is a 2 5 6 -b it Read/W rite Random Access Mem­ ory, organized 256 w ords by one b it. It has ty p ic a l access tim e o f 18 ns and is designed

F10410

Abstract: F10410DC F10405 fairchild ECL
Contextual Info: ECL ISOPLANAR MEMORY F10410 256xl-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N The F 1 041 0 is a 2 5 6 -b it R e a d /W rite Random Access M em ory, organized 256 w ord s by one bit. It has typical access tim e of 18 ns and is

TE1312

Contextual Info: ECL ISOPLANAR MEMORY F10414 256 x 1-BIT FULLY DECODED RANDOM ACCESS MEMORY F A I R C H I L D V O L T A G E C O M P E N S A T E D ECL GENERAL DESCRIPTION - The F10414 is a 256-bit Read/Write random access M em ­ ory, organized 256 words by one bit. It has typical access time of 7 ns and is designed

Contextual Info: ECL ISOPLANAR MEMORY F10410 256x1-BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N — The F 1 0 4 1 0 is a 2 5 6 -b it R e a d /W rite Random Access M em ory, organized 25 6 w ord s by one bit. It has typical access tim e o f 18 ns and is

1117 fairchild

Contextual Info: ECL ISOPLANAR MEMORY F10411 256x1—BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N - The F10411 is a lo w voltage 2 5 6 -b it R e a d /W rite R an­ dom Access M em ory, organized 2 5 6 w ord s by one bit. It has a 2 0 ns typical access tim e

F10405

Abstract: F10411
Contextual Info: ECL ISOPLANAR MEMORY F10411 256x1— BIT FULLY DECODED RANDOM ACCESS MEMORY FAIRCHILD VOLTAGE COMPENSATED ECL G E N E R A L D E S C R IP T IO N - Th e F10 41 1 is a low voltage 256-b it R ead /W rite R a n ­ dom A c c e ss M em ory, organized 2 5 6 w o rd s by one bit. It h as a 2 0 ns typical a c c e ss time

Contextual Info: Philips Components-Signetics 10161 Docum ent No. 8 5 3 -0 6 7 1 E C N No. 99799 D ate of Issue June 14, 1990 Status Product Specification Decoder 1-of-8 Decoder with 3 Enable Inputs Active-LOW Outputs ECL Products PIN CONFIGURATION ORDERING INFORMATION FEATURES

lt 6229

Abstract: lt 6228 10161F 10161N
Contextual Info: 10161 Signetics D ecoder 1-of-8 Decoder With 2 Enable Inputs Active LOW Outputs Product Specification ECL Products DESCRIPTION The 10161 accepts three binary weight­ ed inputs (Ao, A i, A 2 ) and, when en­ abled, provides eight mutualiy-exclusive active LOW outputs (Qo - Q 7 ) • The de­

Contextual Info: ECL ISOPLANAR MEMORY F100414 256 x 1-BIT FULLY DECODED RANDOM ACCESS MEMORY F A IR C H IL D T E M P E R A T U R E AND VOLTAGE C OMPENSATED ECL G E N E R A L D E S C R IP T IO N - The F1 004 14 is a 2 5 6 -b it R ead /W rite Random Access Mem ory, organized 2 5 6 w o rd s by one bit. It has typical access tim e o f 7 ns and is de­

t25 dc he nv

Contextual Info: ECL PRODUCT INFORMATION Test Voltage Values V v ih a MIN Vil a MAX -30 °C +25°C +85°C -0.890 -0.810 -0.700 -1.890 -1.850 -1.825 -1.205 -1.105 -1.035 -1.500 -1.475 -1.440 PARAMETER LOW LEVEL OUTPUT VOLTAGE LOW LEVEL VOH (V) HIGH LEVEL V0 LA <V> THRE8HOLD

signetics 10107

Abstract: decoder active high outputs signetics 10131 ECL 10131 ECL 10102 ECL 10105
Contextual Info: LANSDALE SEMICONDUCTOR bOE J> I 5 3 ^ 3 0 3 O O O Q S m 0^3 « L T E Rating Supply Voltage - Vcc Input Voltage - Vjn SIGNETICS INTEGRATED CIRCUITS Output Source Current 10K ECL Storage Temperature Range Emitter-coupled logic is the fastest logic technology available

32 line demux

Abstract: 10558 E112
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E97 100164 E96 10100/10500 22 {23)(24) ( 1) (2) (3) (4) (5) (9 ) ( 10)(11)(12)(13)(14)(15) ( 16) 1 2 3 4 5 6 7 8 12 13 14 15 16 17 18 19 (8 ) Vcc = Pin 9 (6) VCCA = Pin 10 ( 7 ) Vee = Pin 21 (18) ( -) = DIP

10171

Abstract: 10558 demux pin diagram E112 32 line demux multiplexer 8 2*1
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E11 10172/10572 E10 10171/10571 3 (2) (6) 15 14 2 (3) 15 (2) 14 < 1 1 )7 - (13)8 13 12 11 10 6 5 4 3 (1) (16) (15) (14) (10) (9) (8) (7) <1) (16)05) (14) (10) (9) (8) (7) VCC1 = Pin 1 (5 ) VCC2 = Pin 16 (4)

E108

Abstract: E109 E112 E114 32 line demux
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E108 100165 E109 100160 24 (23) (22) (21) (16) (15) (14) (13) 3 2 1 24 19 18 17 16 (20) 23— ( ) (3) 12 13 14 15 16 17 18 19 20 22 23 24 1 2 3

demux pin diagram

Abstract: 95H90 Fairchild 95H90 fairchild 11c90 10558 pin diagram of 2 to 4 decoder 10164 11C05 11C90 95H16
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E2 95H90/95H91 E1 95H16 3 E3 95010/95016/10010/10016 2 9 5 (13 )9 (15)11 I (11)7 1(14)101 PE ( 10 ) CE (1) 13 CP P0 P i P? P3 TC MR -4 (8 ) Q c 01 0 2 0 3 I 3 (7) | 15 (3) I 12(16) 2 (6 ) 14(2) V c c = P in 4

95H90

Abstract: Fairchild 95H90 95h90 prescaler 95H91 Fairchild 95H90 10/11 11C05 11C90 470 e65 ecl 95h90 prescaler 256
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-ECL E2 95H90/95H91 E1 95H16 3 E3 95010/95016/10010/10016 2 9 5 (13 )9 (15)11 I (11)7 1(14)101 PE ( 10 ) CE (1) 13 CP P0 P i P? P3 TC MR -4 (8 ) Qc 01 0 2 0 3 I 3 (7) | 15 (3) I 12(16) 2 (6 ) 14(2) Vcc = Pin 4 Vcca = Pin 5

multiplexer 30 pin

Abstract: E112 24 pin decoder 5 to 32 demux demux pin diagram 32 line demux
Contextual Info: FAIRCHILD LO GIC/CO N N ECTIO N DIAGRAMS DIGITAL-ECL E49 E50 9579 100155 E51 9580 20 ( 21 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 22 ) ( 23 ) ( 24 ) ( 1 ) 23 24 15 16 17 18 1 2 3 4 mmm 8 9 7 16 15 1 13 11 14 Bo So Ao B i S , A i B2 S2 A s Co ( 19 ) Ci C2 ( 10 ) ( 11 ) ( 9 ) ( 8 ) ( 5 ) ( 4 ) ( 2 ) ( 3 )

32 line demux

Abstract: 5 to 32 demux logic diagram of dual 2 to 4 decoder E112 Decoder 5 to 32
Contextual Info: FAIR C H ILD DIG ITA L ECL 2 T rip le M u ltip le x e r 100171 1 3 3 1.7 3 T rip le M u ltip le x e r 9580 1 3 3.2 Function Item 1 D ual M u ltip le x e r 2.0 3.0 210 2.0 0.8 360 3.2 2.6 300 2.6 260 50 f l Line E50 6B 2.5 200 50 n Line E98 4L,6B ,9B 220 50 f l Line

demultiplexer truth table

Abstract: 10161-F
Contextual Info: 10161-F FEATURES LOGIC DIAGRAM •Fast propagation M ay = 4.0m TYP address to output . 4.5ns TYP enable to output • Low power dissipation = 295 mW/package TYP (no load • High lanout capability — can drive eight 50 Q line« • True parallel decoder — eliminates unequal delay times

SN7404

Abstract: 1 microfarad tantalum capacitor
Contextual Info: TDC1012 TDC1016 Video Speed D/A Converter DA 10-Bit, 20 Msps Description Features The TDC1016 is a bipolar monolithic digital-to-analog converter which can convert digital data into an analog voltage at rates up to 20 Msps Megasamples Per Second . The device includes an input data register and

ic 7404 logic symbol

Abstract: LM 7404 ic
Contextual Info: F A IR C H IL D s e m ic o n d u c t o r w w w .fa irc h ild s e m i.c o m tm TDC1 01 6 V i d e o Sp e e d D/A C o n v e r t e r 1 0 - B i t , 20 M s p s Features Description • • • • • • • • The TDC1016 is a bipolar monolithic digital-to-analog

MSD 7818

Abstract: MN9106 information applikation 7490 N TDA 5700 information applikation mikroelektronik udssr hefte 143KT1 Mikroelektronik Information Applikation K 176 LE, K 561 LN
Contextual Info: In n in ik ü r Q fâ lI Information Applikation RGW Typen­ übersicht + Vergleich TeiM UdSSR JitfÆÊL JUUUUUUL&JJJUL i m i n i ^ r ^ c z l c i c b p o n Information Applikation , 9 H E F T 4 9 * R G W T y p e n ü b e r s i c h t + V e r g l e i c h Teil 1